Browse Title Index

Issue Title
Vol 8, No 3: November 2019 512 bit-SHA3 design approach and implementation on field programmable gate arrays Abstract   PDF
S. Neelima, R. Brindha
Vol 9, No 1: March 2020 6 Transistors and 1 memristor based memory cell Abstract   PDF
Kazi Fatima Sharif, Satyendra N. Biswas
Vol 8, No 3: November 2019 A body bias technique for low power full adder using XOR gate and pseudo NMOS transistor Abstract   PDF
Pritty Pritty, Manoj Kumar, Mariyam Zunairah
Vol 9, No 1: March 2020 A compact graphene based nano-antenna for communication in nano-network Abstract   PDF
M. Saravanan, V.R. Prakash
Vol 9, No 1: March 2020 A compact model of transconductance and drain conductance for DMG-GC-DOT cylindrical gate MOSFET Abstract   PDF
Hind Jaafar, Abdellah Aouaj, Benjamin Iñiguez, Ahmed Bouziane
Vol 10, No 1: March 2021 A design methodology for approximate multipliers in convolutional neural networks: A case of MNIST Abstract   PDF
Kenta Shirane, Takahiro Yamamoto, Hiroyuki Tomiyama
Vol 5, No 3: November 2016 A Gracefully Degrading and Energy-Efficient FPGA Programming using LabVIEW Abstract   PDF
B. Naresh Kumar Reddy, N. Suresh, J.V.N. Ramesh
Vol 9, No 2: July 2020 A hardware system with ARM-based data processing for nano satellites Abstract   PDF
Adrián Stacul, Daniel Pastafiglia, Ariel Di Giovanni, Martín Morales, Sergio Saluzzi, Gerardo García, Agustín Gadea, Ramiro Puga
Vol 10, No 3: November 2021 A low power comparator utilizing MTSCStack, DTTS, and bulk-driven techniques Abstract   PDF
Mohd Tafir Mustaffa
Vol 4, No 3: November 2015 A New-High Speed-Low Power-Carry Select Adder Using Modified GDI Technique Abstract   PDF
M. Anitha, J.Princy Joice, Rexlin Sheeba.I
Vol 11, No 1: March 2022 A novel autonomous remote system applied in agriculture using transmission control protocol Abstract   PDF
Anass Deroussi, Abdessalam Ait Madi, Imam Alihamidi, Lalla Amina Charaf, Mohammed Saber, Anass Erraoui, Adnane Addaim
Vol 2, No 2: July 2013 A Novel Evolutionary Method for Designing Optimized Multifunctional Logic Modules Abstract   PDF
Mehdi Anjomshoa, Ali Mahani
Vol 7, No 2: July 2018 A Novel Face Recognition Algorithm Using Gabor - based KPCA Abstract   PDF
Umasankar Ch, D. Naresh Kumar, Md. Abdul Rawoof, D. Khalandar Basha, N. Madhu
Vol 1, No 1: March 2012 A Novel FPGA based Leading One Anticipation Algorithm for Floating Point Arithmetic Units Abstract   PDF
Ashwini Suresh Deshmukh
Vol 1, No 1: March 2012 A Novel High Speed FPGA Architecture for FIR Filter Design Abstract   PDF
Sachin B. Jadhav, Nikhil Niwas Mane
Vol 7, No 2: July 2018 A Power Efficient Self Biased OTA Design Based on g_m/I_D Methodology with Considering Load Variation, Temperature Variation and Power Supply Variation Abstract   PDF
Vikas Mittal
Vol 8, No 3: November 2019 A scalable FPGA based accelerator for Tiny-YOLO-v2 using OpenCL Abstract   PDF
Yap June Wai, Zulkanain Mohd Yussof, Sani Irwan Md Salim
Vol 9, No 2: July 2020 A system verilog approach for verification of memory controller Abstract   PDF
Sowmya K B, Gagana P
Vol 10, No 3: November 2021 ACCESS - IoT enabled smart lock Abstract   PDF
Harshith Gadupu, Osa Mokharji, Raunak Kankaria, Shrey Kumar, Kayalvizhi Jayavel
Vol 1, No 2: July 2012 AES Encryption Algorithm Hardware Implementation: Throughput and Area Comparison of 128, 192 and 256-bits Key Abstract   PDF
Samir El Adib, Naoufal Raissouni
Vol 5, No 1: March 2016 An Automated Way of Baking Process for Moisture Sensitive Components Abstract   PDF
A. Ramamoorthy, M. Jagadeeshraja, L. Manivannan, K. Raja
Vol 4, No 3: November 2015 An Efficient approach for Design and Testing of FPGA Programming using LabVIEW Abstract   PDF
Naresh Kumar Reddy, N. Suresh
Vol 4, No 2: July 2015 An Efficient Framework for Floor-plan Prediction of Dynamic Runtime Reconfigurable Systems Abstract   PDF
Ahmed Al-Wattar, Shawki Areibi, Gary Grewal
Vol 2, No 3: November 2013 An Efficient Implementation of the Entire Transforms in the H.264/AVC Encoder using VHDL Abstract   PDF
Farhad Rad, Ali Broumandnia
Vol 11, No 1: March 2022 An efficient multi-level cache system for geometrically interconnected many-core chip multiprocessor Abstract   PDF
Tirumale Ramesh, Khalid H Abed
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