Editorial Policies

Focus and Scope

The International Journal of Reconfigurable and Embedded Systems (IJRES) aims to provide a forum for academics, industrial professionals, educators, and policymakers working in the field to contribute and disseminate innovative and significant new work on reconfigurable systems, embedded systems, very large-scale integration (VLSI) design, and the internet of things (IoT). The IJRES covers all aspects of reconfigurable systems, field programmable gate arrays, embedded computing, and embedded IoT devices, including algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications, embedded architectures, systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC), multi-processor systems on a chip (MPSoC), and network-on-chip (NoC) which covers, but not limited to, the following scope:

Reconfigurable System

  • Applications and design studies: implementation of novel designs on FPGAs establishing state-of-the-art in high-performance, low-power, security, or high-reliability. Designs leveraging unique capabilities of FPGA architectures or demonstrating significant improvements over alternative programmable technologies (e.g., CPU, GPU). Design studies or architecture explorations enabling improvement of FPGA architectures.
  • Applications: security and cryptography; time sensitive/critical networks; big data, HPC, event processing; embedded computing and DSP; robotics, space, bioinformatics, automotive; safety and mission critical systems; deep learning and neural network
  • Approximate computing in FPGAs
  • Architectures: self-adaptive, evolvable; heterogeneous; low-power designs; approximate computing; fine-/coarse-/mixed-grained; embedded MPSoCs; interconnect (NoCs, …); resilient and fault tolerant
  • Benchmarks and evaluations; benchmarks-compute performance and/or power/cost efficiency in cloud/HPC; area, energy, and performance evaluation; comparative analysis of heterogeneous devices and frameworks for HPC
  • Cad for FPGAs: algorithms for synthesis, technology mapping, logic and timing optimization, clustering, placement, and routing of FPGAs. Novel design software for system-level partitioning, debug, and verification. Algorithms for modeling, analysis and optimization of timing and power.
  • CAD for FPGAs: Placement, routing, retiming, log
  • Communication aware multiprocessor embedded systems
  • Communication centric design techniques at different abstraction levels
  • Compilation and programming languages
  • Design methods and tools: high-level languages and compilation; simulation and synthesis-estimation techniques; design space exploration; run-time systems and virtualization
  • Design space exploration (DSE) of reconfigurable and/or NoC-based systems; and self-reconfiguration and self-optimization for HPC
  • Design-flows for HHPC and HPRC
  • Domain specific languages (DSLs) for HHPC and HPRC; high-level and pure software programming for reconfigurable devices
  • Domain specific languages that target FPGAs
  • DSLs for HHPC and HPRC
  • FPGA architecture: architectures for programmable logic fabrics or their components, including routing, flexible logic cells, embedded blocks (memory, DSP, processors), and i/o interfaces. Novel commercial architectures and architectural features.
  • FPGA Architecture: novel logic block architectures; combination of FPGA fabric and system blocks (DSP, processors, memories, etc.); design of routing fabric; I/O interfaces; new commercial architectures and architectural features.
  • FPGA circuit design: circuits and layout techniques for the design of FPGAs. Impact of future process and design technologies on FPGAs as well as novel memory memory or nano-scale devices. Methods for analyzing and improving static and dynamic power, power and clock distribution, yield, manufacturability, security, reliability, and testability.
  • FPGA Circuit Design: novel FPGA circuits and circuit level techniques, impact of process and design technologies, methods for analyzing and improving issues with soft errors, leakage, static and dynamic power, clocking, power grid, yield, manufacturability, reliability, test; studies on future device technologies (e.g. nanoscale, 3D gate) for FPGAs.
  • FPGA compilation of legacy codes
  • FPGA technology: novel FPGA architectures and circuits; advances in CAD tools for FPGAs, in areas such as technology mapping, placement, routing, and others; high level design methodologies that permit FPGA design at higher levels of abstraction; and new applications for FPGAs, particularly for energy efficient and high-performance computation.
  • FPGA-based and FPGA-like computing engines: systems and software for compiled accelerators, reconfigurable/adaptive computing, and rapid-prototyping. Programmable overlay architectures implemented using FPGAs.
  • FPGAs and reconfigurable computing for software programmers
  • FPGAs and reconfigurable hardware accelerators for HPC, cloud and machine learning
  • FPGAs and reconfigurable hardware for internet of things (IoT)
  • Heterogeneous high-performance computing (HHPC) and high-performance reconfigurable computing (HPRC) applications: HPC applications on multi/many-core CPUs, GPUs and FPGAs; HHPC and HPRC for scientific applications; HHPC and HPRC for machine learning and artificial intelligence; HHPC and HPRC for big-data applications; FPGAs for edge computing and bump-in-the-wire
  • High-level abstractions and tools for FPGAs: general-purpose and domain-specific languages, tools, and techniques to facilitate the design, debugging and verification of FPGA-based applications and systems. Novel hardware/software co-design and high-level synthesis methodologies enabling digital signal processing, compute acceleration, networking, machine learning, and embedded systems.
  • Industrial case studies applying the topics above to domains such as HPC, networking, telecom, cloud computing and transportation systems.
  • Industrial case studies: HPC, routers, mobile systems, transportation system, etc.
  • Just in time hardware synthesis
  • Low power design of reconfigurable and multiprocessor socs
  • Networks and NoCs: novel NoC architectures for high-performance systems; systems software support for advanced NOC-based systems; NoC-aware compilation and runtime systems; mapping and scheduling for NoC-based systems; implementation case studies of reconfigurable and NoC-based systems
  • New paradigms for communication centric, adaptive and reconfigurable computing
  • On chip communication architectures (buses and networks on chip NoCs)
  • OS and middleware for reconfigurable and multicore SoCs
  • Other: reliability, scalability, availability, and fault tolerance; reconfigurable computing education
  • Performance portability between CPU, GPU, and FPGA based systems
  • Performance portability between different FPGA platforms
  • Programming productivity for FPGAs
  • Reconfigurable and adaptive embedded socs
  • Reconfigurable computing
  • Reconfigurable platforms
  • Reconfigurable system-on-chip
  • Reconfigurable system design and verification
  • Runtime thermal and power management
  • Specification languages and design methodologies
  • Targeting FPGAs in the cloud
  • Toolchains for compiling DSLs to FPGAs
  • Tools, languages, frameworks, benchmarks, and DSE
  • Trends (in): teaching RC; surveys and future trends; benchmarks; emerging technologies; cyber-physical systems
  • Verification and evaluation techniques
  • VMs, middleware, run-time and operating systems for HHPC and HPRC

Embedded System

  • 8051 microcontroller programming
  • 8051 based advanced embedded systems design
  • Advance embedded signal and image processing
  • Advance signal and image processing
  • Advanced computer architecture
  • Advanced embedded system design
  • Application-specific processors/ devices
  • ARM Cortex-M series programming
  • ARM based advanced embedded systems design
  • AVR based advanced embedded systems design
  • C programming language for embedded applications
  • Controller area network (CAN) and CAN access programming language (CAPL)- CAN and CAPL programming
  • Digital signal processors and architectures
  • Digital system design
  • Embedded access technologies
  • Embedded automotive systems
  • Embedded computing
  • Embedded computing education
  • Embedded design cycle
  • Embedded hardware
  • Embedded hardware support
  • Embedded instrumentation and control
  • Embedded Linux
  • Embedded networking
  • Embedded of things
  • Embedded operating systems
  • Embedded programming languages
  • Embedded real time operating systems
  • Embedded signal and image processing
  • Embedded software
  • Embedded system
  • Embedded system architecture
  • Embedded testing techniques
  • Emerging technologies and applications
  • Emerging technologies/applications/principles
  • FPGA based embedded system design
  • Hardware/software co-design
  • Micro-controller based embedded systems design
  • Microcontrollers for embedded system design
  • Multimedia and signal coding
  • Network security and cryptography
  • Pic based advanced embedded systems design
  • Raspberry Pi
  • Real time embedded systems
  • Real-time operating system (RTOS) Programming
  • Sensors and actuators
  • Smart card technologies
  • Soft computing techniques
  • Wireless communications and networks

VLSI Design

  • Advanced computational methods
  • Advanced computer architecture
  • Advanced CPLD based design
  • Advanced digital design
  • Advanced FPGA based design
  • Algorithms for VLSI design automation
  • Analog VLSI design
  • Analog and digital IC design
  • Analysis and design of digital systems using VHDL
  • Application-specific processors and devices
  • Business applications
  • CMOS sensors
  • Component and binding models
  • Device, circuit and systems
  • Hardware and software co-design
  • IC fabrication and testing
  • Industrial practices and benchmark suites
  • Integration with business logic
  • Integration with SOA
  • Micro electro mechanical system
  • Middleware
  • Multi-valued logic (MVL) circuits
  • Nano-electronics devices
  • Networked embedded systems
  • Policy-based management
  • Programming abstractions
  • Recent trends
  • Service-oriented architectures
  • Testing techniques
  • VLSI design and IC technology
  • VLSI for bio-engineering
  • VLSI for ESDM
  • VLSI for instrumentation-s and controls
  • VLSI for wireless communications 5G and beyond
  • VLSI signal processing
  • Asynchronous system design
  • CMOS rf circuit design
  • Computational methods for VLSI
  • Computer aided VLSI design
  • Cryptology and crypto chip design
  • Data structure and algorithm analysis
  • Design of VLSI system
  • Digital image processing for VLSI
  • Digital logic with Verilog
  • Digital signal processing structures for VLSI
  • Digital system design
  • Electronic design automation tools
  • Electronic packaging
  • Embedded systems: high-level synthesis for VLSI systems
  • Functional and formal verification
  • Hardware-software co-design
  • HDL languages used for VLSI: Verilog and VHDL
  • HDL modelling
  • Low power VLSI design
  • Mems and IC integration
  • Mixed - signal circuit design
  • Modelling and synthesis with Verilog HDLMOS circuit design
  • Nano technology
  • PCB designing
  • Process, devices and circuit simulation
  • RF and bio MEMS
  • Simulation, synthesis and verification of integrated circuits and systems
  • Solid state electronics devices
  • System on programmable chip design
  • Thermal design of electronic equipment
  • VLSI architectures, algorithms, methods and tools for modelling
  • VLSI process technology
  • VLSI system testing
  • VLSI test and testability

Embedded Internet of Things (IoT)

  • Application-specific hardware designs for IoT
  • Case study for cybersecurity, privacy risks, safety and reliability
  • Connectivity and programming of IoT device using wireless transport and MQTT protocol    
  • Constrained application protocol (CoAP)
  • Design principles and methodologies used in IoT systems
  • Edge computing using embedded devices
  • Efficient and accurate machine learning usage with embedded devices
  • Embedded system design addressing one or more of the following IoT issues: energy-efficiency, resiliency, scalability, longevity, cost, device heterogeneity, and standardization
  • Emerging IoT applications using new generation embedded devices
  • Evolution and technologies used in IoT
  • Explore IoT security laws
  • Firmware design and development methodologies
  • Hardware design for IoT
  • Hardware–software co-design for IoT systems and applications
  • Illustration and evolution of 5G myriad IoT applications including smart cities, water waste, and agriculture
  • IoT applications
  • IoT cloud architecture, primarily Azure  
  • IoT embedded system programming, sensors and components
  • IoT security
  • IoT stacks and usage on sensors
  • IPv6 low-power personal area networks (6LoWPAN)
  • Lightweight application-layer service discovery protocol
  • Microcontroller design and performance analysis within IoT applications
  • Middleware for embedded systems
  • New sensor/actuator design for IoT
  • Novel security and privacy methods leveraging embedded device hardware and/or software
  • Real-time data analytics using embedded devices
  • Routing protocol for Low power lossy networks (RPL)
  • Simple service location protocol (SSLP)
  • Telematic networks
  • WebLogic web services: Representational state transfer (REST) and Java API for RESTful web services (JAX-RS)
  • Wireless sensor network design and implementation for IoT systems


Section Policies


Peer Review Process

This journal has a standard single-blind review policy, which means that the name of the reviewer is never shown to the person who submitted the paper. Authors should present their papers honestly, without making stuff up, lying, plagiarizing, or manipulating data in the wrong way. Referees who don't know who wrote the paper judge it based on its contribution, originality, relevance, and presentation. Papers will be sent to at least two reviewers, who may be members of the Editorial Board or other experts in the field, who will look at them anonymously. In order to speed up the review process and get back to authors quickly, editors may triage a submission and make a decision without sending the paper out for external review. The Editor will let you know as soon as possible, hopefully in 6–12 weeks, how the review went. The Editors' decision is final, and they will not respond to letters about manuscripts they think are not right for this journal. All messages, including requests for changes and notices of what the editors have decided, will be sent by email.


Open Access Policy

This journal adhere to the best practice and high publishing standards and comply with the following conditions:

  1. Provides immediate open access to its content on the principle that making research freely available to the public supports a greater global exchange of knowledge;
  2. Allows the author to hold the copyright and to retain publishing right without restrictions;
  3. Deposits content with a long term digital preservation or archiving program;
  4. Uses DOIs as permanent identifiers;
  5. Embeds machine-readable CC licensing information in articles;
  6. Allows generous reuse and mixing of content, in accordance with CC BY-SA license;
  7. Can Provide article level metadata for any indexers and aggregators;
  8. Has a deposit policy registered wíth a deposit policy registry, e.g. Sherpa/Romeo.



This journal utilizes the LOCKSS system to create a distributed archiving system among participating libraries and permits those libraries to create permanent archives of the journal for purposes of preservation and restoration. More...


Publication Ethics and Malpractice Statement

The Institute of Advanced Engineering and Science (IAES) is a non-profit international scientific association of distinguished scholars engaged in engineering and science devoted to promoting research and technologies in engineering and science fields through digital technology. IAES journals are peer-reviewed international journals. This statement clarifies the ethical behavior of all parties involved in the act of publishing an article in our journals, including the authors, the editors, the peer-reviewers, and the publisher (Institute of Advanced Engineering and Science). This statement is based on COPE’s Best Practice Guidelines for Journal Editors.

Click here for more information on Research and Publication Ethics.


Checklist for preparing your paper for publication

To speed up your paper's publication, kindly follow the guidelines below:

1. Is your manuscript up to the required standards? (written in English; at least 4 pages long; no more than 20 pages; use EndNote, Mendeley, or Zotero for reference management and formatting; use IEEE style)

2. Is the format of your manuscript IJRES? It is crucial that you adhere to every aspect of the IJRES format at this point. Please make an effort to adhere to the format (http://iaescore.com/gfa/ijres.docx) as precisely as you can.

3. Is your abstract written properly and does your title make sense? Maximum 10 words in the title, no acronyms or abbreviations. The Abstract (MAX 200 WORDS) should be informative and fully self-explanatory (no citation in abstract), and it should clearly describe the issue at hand, suggest a course of action, and highlight key results and conclusions.

4. It is advised that authors provide their papers in the following sections: 1. Introduction - 2. The Proposed Method/Algorithm/Procedure specifically designed (optional) - 3. Research Method - 4. Results and Discussion – 5. Conclusion. After the introductory part, authors may provide intricate theorem proofs or obscure evidence for the soundness of algorithms (obvious theorems & straightforward proofs of existing theorems are NOT needed).

5. Introduction section: Explain the study's context and specify the specific goal in the introduction section. Within three to seven paragraphs, an introduction should provide the following three components:
    - Background: The context must be made explicit by authors. Authors should, ideally, provide an overview of the state-of-the-art in the subject area of the report.
    - The Problem: If there were no issue, there would be no need to write a text and certainly no need to read it. Please provide readers with a reason to continue reading. Experience has shown us that a few lines are frequently enough for this section.
    - The Proposed Solution: Now and only now! The contribution of the text may be described by the authors. Here, authors must make sure that readers identify the new parts of their work.
    - By citing pertinent works, authors should set the study in its right perspective. In this section, at least 15 references (current journal publications) are utilized.

6. Method section: The experimental procedures should be presented in a way that makes them easy for other scientists to replicate. It should be clear and comprehensive in every way.

7. Results and discussion section: Results should be presented in an easy-to-understand manner. The most significant findings are presented in this part, together with comparisons to other research findings and, when applicable, the outcomes of statistical analysis. It is not advisable to repeat results from figures in tables. Here, the author(s) should explicitly state what they learned throughout their investigation. It need to be logically organized and clearly set out. Appropriate references should be used to support this section.

8. Conclusion section: Summarize in a paragraph the main findings of the investigation. Are the results supporting the statements in this section, and do they seem reasonable? Have the authors explained how the findings compare to what was anticipated and to past research? Does the article refute or reinforce preexisting theories? Does the analysis of the research's impact on the field of science's body of knowledge?

9. Language. Understanding the science may be made more challenging by articles that are poorly written or contain grammatical errors.

10. Please confirm the document is current. It is anticipated that 10–20% of references will be to current studies.

11. Is the writing in the text clear? The article is intriguing. Does the information flow smoothly from one area to the next? Please strive to maintain the appropriate level for your text. It should be simple enough for highly skilled experts to grasp, but please refrain from discussing well-known information (use proper references instead). Negative evaluations for papers frequently result from the reviewers' inability to grasp the text, which is the authors' (not the reviewers') problem. There is no need to publish the work if reviewers have problems since other readers will have the same issue.

12. Are your references sufficient? Depending on the length of the manuscript, we will typically want a minimum of 15 to 25 references, the majority of which should be to academic articles. Textbook citations should be used extremely sparingly, and web page citations should be avoided. The text of the document should include references to all cited articles.

13. Tables and figures. Relationship between Tables or Figures and Text: All tables and figures should be cited in the content since they support the text. Don't put tables and figures before when they are first mentioned in the text. The reader should be made aware of what to look for while utilizing the table or figure, according to the authors. Leave the reader to independently investigate the specifics and simply highlight the key takeaway that the reader should be able to get from them.
    a. All figures appearing in article must be numbered in the order that they appear in the text.
    b. Each figure must have a caption fully explaining the content
    c. Figure captions are presented as a paragraph starting with the figure number i.e. Figure 1, Figure 2, etc.
    d. Figure captions appear below the figure
    e. Each figure must be fully cited if taken from another article
    f.  All figures must be referred to in the body of the article
    a. Material that is tabular in nature must appear in a numbered captioned table.
    b. All tables appearing in article must be numbered in the order that they appear in the text.
    c. Each table must have a caption fully explaining the content with the table number  i.e. Table 1, Table 2, etc.
    d. Each column must have a clear and concise heading
    e. Tables are to be presented with single horizontal line under: the table caption, the column headings and at the end of the table.
    f. All tables must be referred to in the body of the article
    g. Each table must be fully cited if taken from another article

14. Each citation has to be enclosed in square brackets and listed in the text in the order that it appears. For instance, the first citation [1], the second citation [2], the third and fourth citations [3], [4]. The ideal approach for referencing many sources at once is to state each number separately, in its own brackets, with a comma or dash between numbers, as in [1], [3], [5], or [4]-[8]. The in-text citation does not need to include the author's last name, the pages that they utilized, or the publication date. Instead, cite the source using a number enclosed in square brackets, such as [9], which will then match to the whole citation in your reference list. Examples of in-text citations:
        This theory was first put forward in 1970 [9]."
        Sutikno [10] has argued that...
        Several recent studies [7], [9], [11]-[15] have suggested that....
        ...end of the line for my research [16].
15. Self-citations: This journal requests that authors limit their use of self-citation in order to prevent citation manipulation (COPE, 2019). We highly advise limiting the number of self-citations to either 5 (including jointly produced papers) or 20%, whichever is lower.

16. Please be aware that you will be required to modify your paper so that the last page is not partially empty for the final submission of normal paper.



Authorship provides credit for a researcher's contributions to a study and carries accountability. 

IJRES considers individuals who meet all of the following criteria to be authors:

  • Made a significant intellectual contribution to the theoretical development, system or experimental design, prototype development, and/or the analysis and interpretation of data associated with the work contained in the article.
  • Contributed to drafting the article or reviewing and/or revising it for intellectual content.
  • Approved the final version of the article as accepted for publication, including references.

Each author has given their approval to the submitted version (as well as any significantly updated version involving the author's contribution to the study).

Each author has agreed to be personally accountable for his or her own contributions as well as to ensure that any questions about the accuracy or integrity of any part of the work, even if the author was not personally involved, are appropriately investigated, resolved, and documented in the literature.

IJRES does not need all authors of a research article to sign the letter of submission, nor does the list of authors have to be in any particular order. When an article is submitted to IJRES, it is assumed that all of the stated authors have agreed on all of the contents, including the author list and author contribution declarations. The corresponding author is responsible for ensuring that this agreement has been reached, that all authors have agreed to be so listed, and that the manuscript submission to the journal has been approved, as well as for managing all communication between the journal and all co-authors, both before and after publication. The corresponding author is also in charge of filing a conflicting interests statement on behalf of all paper authors.

It is expected that the corresponding author (and on multi-group collaborations, at least one member of each collaborating group, usually the most senior member of each submitting group or team, who accepts responsibility for the contributions to the manuscript from that team) will be responsible for the following with respect to data, code and materials:

  • ensuring that data, materials, and code comply with transparency and reproducibility standards of the field and journal;
  • ensuring that original data/materials/code upon which the submission is based are preserved following best practices in the field so that they are retrievable for reanalysis;
  • confirming that data/materials/code presentation accurately reflects the original;
  • foreseeing and minimizing obstacles to the sharing of data/materials/code described in the work
  • ensuring that all authors (or group leaders in multi-lab collaborations) have certified the author list and author contributions

Author lists should be carefully considered before submission. At submission, the corresponding author must include written permission from the authors of the work concerned for mention of any unpublished material cited in the manuscript (for example others' data, in press manuscripts, personal communications, or work in preparation). The corresponding author also must clearly identify at submission any material within the manuscript (such as figures) that has been published previously elsewhere and provide written permission from authors of the prior work and/or publishers, as appropriate, for the re-use of such material.

After acceptance, the corresponding author is responsible for the accuracy of all content in the proof, including the names of coauthors, addresses, and affiliations. Changes to the author list post-acceptance are not allowed.

The corresponding author is the point of contact for questions concerning the published work after it has been published. It is their responsibility to notify all co-authors of any issues that arise in connection with the published paper and to ensure that such issues are resolved as soon as possible. It is the obligation of the authors of published content to notify the journal as soon as they become aware of any features that need to be corrected.

All authors must agree before making any changes to the author list after submissions, including any changes to the order of the authors or the removal or addition of any authors. Editors of the IJRES are unable to look into or resolve authorship issues before or after publication. If such disputes cannot be settled between the authors, they should be brought to the attention of the appropriate institutional authorities.

The primary affiliation for each author should be the institution where the majority of their work was done. If an author has subsequently moved, the current address may also be stated.


Plagiarism Detection Policy

The peer-review process is the heart of scientific publishing. As part of its mission to protect the integrity of the scholarly record, Institute of Advanced Engineering and Science (IAES) feels a strong obligation to help the scientific community with all aspects of research and publishing ethics. All submitted manuscripts must have original content. Before sending their manuscript to the journal, all authors are asked to check for plagiarism using software (please use iThenticate or Turnitin to check the similarity). Editors will also use the software Turnitin or iThenticate to see if any of the manuscripts in this journal are too similar to others. If plagiarism is found or indicated, the manuscript will be immediately rejected.

The similarity rate will be checked again on the final camera-ready version. Overall, a manuscript shouldn't have more than 25 percent of similarities, and a single source shouldn't have more than 10 percent of similarities.


Retraction and Correction Policy

Institute of Advanced Engineering and Science (IAES) is committed to maintaining the integrity and completeness of our material for end users. After online publication, articles can only be edited as described below. IAES values the authority of published publications and bases its policies on best standards in academic publishing. An Erratum is a declaration by the original paper's authors that briefly summarizes any corrections. Any implications on paper conclusions should be acknowledged. The revised article remains available with an erratum notice. Erratum is free and linked to the corrected article. A Retraction means the paper is no longer scientifically valid. Retractions are issued if there is clear proof that the findings are unreliable due to misbehavior or honest error, if the findings have been published elsewhere without proper reference, permission, or justification, if the work is plagiarized, or if the work reports unethical research. The retracted article is not deleted from the online journal to safeguard the record, but notification of retraction is issued, made publicly available to all readers, and linked to the retracted article. When writers find significant scientific flaws, they can publish a retraction; otherwise, the Editors or Publisher may do so. All retractions state the rationale and who made the decision. A retraction without author consensus is also indicated. In circumstances of legal infringement, the Publisher may redact or delete an article. Bibliographic information will be kept to protect the scientific record. A Publisher's Note alerts readers to article corrections. It is provided by the Publisher when typographical or production issues influence the article metadata (such as title, author list, or byline) or the reader's ability to understand the content. The original article has been replaced. Everyone can read the publisher's notes. The Publisher may repair minor errors that do not alter the metadata or a reader's ability to understand an article and do not entail a scientific inaccuracy or omission. The original article is removed and replaced with a correction. Corrections are indicated on the article. The original article can only be withdrawn and replaced with a rectified version within a year of its publication date. An article with an older publication date will simply include a Publisher's Note. The following guideline may also be helpful: COPE Guidelines for Retracting Articles.


Withdrawal of Manuscripts

The author is not permitted to withdraw submitted papers since doing so wastes important resources such as time spent by editors and referees processing submitted manuscripts, as well as money and labour invested by the publisher. If the author still seeks removal of his/her manuscript while it is still being peer-reviewed, the author will be fined $200 per manuscript as a withdrawal penalty to the publisher. It is, nevertheless, unethical to remove a submitted paper from one publication if it has been accepted by another. If a manuscript is withdrawn after it has been accepted for publication, the author will be fined $500 per manuscript. The manuscript may be withdrawn only once the withdrawal penalty has been fully paid to the Publisher. If the author refuses to pay the penalty, the author and his or her connection will be barred from future publishing in this journal. His/her previously published papers will also be deleted from our web database.