Vol 8, No 3

November 2019

DOI: http://doi.org/10.11591/ijres.v8.i3

Table of Contents

Designing ALU using GDI method
Mohammadreza Fadaei
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151-161
A body bias technique for low power full adder using XOR gate and pseudo NMOS transistor
Pritty Pritty, Manoj Kumar, Mariyam Zunairah
PDF
162-168
512 bit-SHA3 design approach and implementation on field programmable gate arrays
S. Neelima, R. Brindha
PDF
169-174
Design and implementation of CNTFET based ternary 1x1 memories
S.Tamil Selvan, M. Sundararajan
PDF
175-184
Design and Implementation of Reduced Power Energy Efficient Binary Coded Decimal Adder
N. Saravanakumar, K. Sakthi Sudhan, K. N. Vijeyakumar, S. Saranya
PDF
185-193
Performance evaluation of an efficient five input majority gate design in QCA nanotechnology
Amanpreet Sandhu, Sheifali Gupta
PDF
194-205
A scalable FPGA based accelerator for Tiny-YOLO-v2 using OpenCL
Yap June Wai, Zulkanain Mohd Yussof, Sani Irwan Md Salim
PDF
206-214