Vol 4, No 3

November 2015

DOI: http://doi.org/10.11591/ijres.v4.i3

Table of Contents

Development of BSP for ARM9 Evaluation Board
Vinayak Pandit K., Sanket Dessai, Shilpa Chaudhari
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161-172
A New-High Speed-Low Power-Carry Select Adder Using Modified GDI Technique
M. Anitha, J.Princy Joice, Rexlin Sheeba.I
PDF
173-177
Design of Low Power Dual Dynamic Node Flip-Flop Using Sleep Transistor with NMOS
Ajeesh Kumar, N. Saraswathi
PDF
178-184
NIOS II Based Secure Test Wrapper Design for Testing Cryptographic Algorithms
Chakrapani Kannan
PDF
185-191
An Efficient approach for Design and Testing of FPGA Programming using LabVIEW
Naresh Kumar Reddy, N. Suresh
PDF
192-200
Dynamic Partial Reconfiguration with FIR Filter Application
Noopur Astik
PDF
201-208
Design and Implementation of Recursive Least Square Adaptive Filter Using Block DCD approach
Sachin S. Khanande, S.J. Honade
PDF
209-212
Design and Implementation of Four Bit Binary Shifter Circuit Using Reversible Logic Approach
Vandana Shukla, O. P. Singh, G. R. Mishra, R. K. Tiwari
PDF
213-218