A fast half-subtractor using 8T static random access memory for in-memory computation

Abstract

The existing system for computation completely incorporates Von-Neumann architecture which has limitations with respect to its memory, parallelism and power constraints. This has affected the efficiency of the computing system. Novel architectural solutions are required to meet the growing demands for improved computational efficiency and power management in very large scale integration (VLSI) systems. To deal with the large-scale data, computation in memory (CIM) has been introduced. The paper presents the half subtractor circuit and the In-memory computation co-design using eight transistors static random access memory (SRAM) cell whose read circuitry is transmission gate based. The proposed half-subtractor with the CIM is implementation is carried out in 180 nm complementary metal– oxide–semiconductor (CMOS) technology. The sensing scheme used is the latch-based sense amplifier along with the 8T SRAM cell. The proposed SRAM with transmission-gate based read circuitry along with latch-based sense amplifier reduces the delay and power consumed during the read operation significantly and a bit reduction during the write operation. The static noise margin (SNM) for read operation has been increased by 9% in the transmission gate-based SRAM as compared to conventional 8T SRAM. The delay of the proposed design has been reduced by 53% during the read operation and 4.43% during the write operation. The power consumed has been reduced by 3% and 8.6% during read and write operations, respectively.