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Home > Archives > Vol 10, No 2

DOI: http://doi.org/10.11591/ijres.v10.i2

Table of Contents

Cost-efficient reconfigurable geometrical bus interconnection system for many-core platforms Tirumale Ramesh, Khalid Abed

PDF 77-89

Smart helmet using internet of things Mohamed A. Torad, Mustafa Abdul Salam

PDF 90-98

FPGA implementation of Lempel-Ziv data compression Gody Mostafa, Abdelhalim Zekry, Hatem Zakaria

PDF 99-108

Co-simulation of linear congruential generator by using Xilinx system generator and MATLAB Simulink Suneeta Suneeta

PDF 109-114

Implementation of video surveillance system using embedded Blackfin processor Sanket Dessai, Deepa Kannan, Shiva Prasa Yadav

PDF 115-122

Comparing reliabilities of centralized and distributed switching architectures for reconfigurable 2D arrays Behrooz Parham

PDF 123-129

Restoration circuits for low power reduce swing of 6T and 8T SRAM cell with improved read and write margins Ram Murti Rawat, Vinod Kumar

PDF 130-136

Processor performance metrics analysis and implementation for MIPS using an open source OS Varuna Eswer, Sanket Dessai

PDF 137-148

An internet of things belief rule base smart system to predict earthquake Md. Mahashin Mia, Abdullah Al Hasan, Rahman Atiqur, Rashed Mustafa

PDF 149-156