Vol 7, No 3

November 2018

DOI: http://doi.org/10.11591/ijres.v7.i3

Table of Contents

An Optimal Design of CMOS Two Stage Comparator Circuit using Swarm Intelligence Technique
Sasikumar Sasikumar, Muthaiah Muthaiah
PDF
131-137
Real time FPGA Implementation of PWM Chopper Fed Capacitor Run Induction Motor
N. Murali, V. Balaji
PDF
138-148
Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology
T. Kanthi, D. Sharath Babu Rao
PDF
149-156
High Speed Area Efficient FPGA Implementation of AES Algorithm
P. B. Mane, A. O. Mulani
PDF
157-165
Design Considerations of Reconfigurable CMOS Mixers for Multi-Standard Communication Receiver Systems
Manoj Kumar Vishnoi, Satya Sai Srikant
PDF
166-172
Design and Implementation of a New Architecture of a Real-Time Reconfigurable Digital Modulator (DM) Into QPSK, 8-PSK, and 16-PSK on FPGA
Walder Andre, Olivier Couillard
PDF
173-185
Design and Implementation of LCG-Trivium Key Stream Generator into FPGA
Tchahou Tchendjeu A. E, Tchitnga Robert, Fotsin Hilaire B
PDF
186-194
New Optimized Reconfigurable ALU Design Based on DG-CNTFET Nanotechnology
Houda Ghabri, Dalenda Ben Issa, Hekmet Samet
PDF
195-202
Energy and Area Effective Hardware Design of Lifting Approach Discrete Wavelet Transform
Khamees Khalaf Hasan, Ibrahim Khalil Salih, Abdumuttalib. A. Hussen
PDF
203-214