FPGA implementation of high-performance Huffman encoder for image processing applications

Abstract

An optimized Huffman encoder is essential in all applications where it is necessary to achieve the best performance, such as audio coding, data encryption, data compression, and image processing applications. This article presents a space-optimized encoding scheme to maximize performance and minimize latency in Dual Huffman encoding. The proposed approach employs dynamic tree selection using Dual Huffman encoding. A Dual Huffman code with dynamic tree selection can be run in parallel to support high-throughput applications. The resulting design optimally creates the Huffman dual encoding. This codeword table is based on a dynamic tree generation and selection algorithm, leading to a faster encoding process with lower latency. The architecture was developed using Vivado Xilinx 2023.2 and tested on three different field programmable gate array (FPGA) platforms (Zynq 7045, Zynq 7100, and Kria KV260 AI Vision board). A performance comparison between devices demonstrates that the Kria KV260 had the lowest latency (100 ns), as opposed to the Zync 7045 and Zynq 7100, which had latencies of 200 ns and 150 ns, respectively. These results elucidate the scalability of the architecture and its suitability for real-time image compression. When implemented on the Kria KV260, the dynamic tree selection-based Dual Huffman encoder is capable of fast, parallel image compression. The compression makes it a good candidate for advanced FPGA-based image processing systems with internet of things (IoT) applications.