Pritty, Pritty, Guru Gobind Singh Indraprastha University, India

• Vol 8, No 3: November 2019 - Other articles
  A body bias technique for low power full adder using XOR gate and pseudo NMOS transistor
  Abstract  PDF

This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

International Journal of Reconfigurable and Embedded Systems (IJRES)
p-ISSN 2089-4864, e-ISSN 2722-2608
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).