Vol 7, No 2

July 2018

DOI: http://doi.org/10.11591/ijres.v7.i2

Table of Contents

Notice of Retraction Designing of Vedic Based Modulo Multiplication in Residue Number System
Shamim Akhter, Divya Bareja, Satyendra Kumar
67-73
Berger Code Based Concurrent Online Self-Testing of Embedded Processors
G. Prasad Acharya, M. Asha Rani
PDF
74-81
FPGA Implementation of DTCWT and PCA Based Watermarking Technique
M. S. Sudha, T. C. Thanuja
PDF
82-90
Impacts of Embedded Generation on Distribution Network Behavior
Puladasu Sudhakar, Sushama Malaji, B. Sarvesh
PDF
91-103
A Power Efficient Self Biased OTA Design Based on g_m/I_D Methodology with Considering Load Variation, Temperature Variation and Power Supply Variation
Vikas Mittal
PDF
104-114
Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders
Nehru.K K, Nagarjuna T, Somanaidu U
PDF
115-123
A Novel Face Recognition Algorithm Using Gabor - based KPCA
Umasankar Ch, D. Naresh Kumar, Md. Abdul Rawoof, D. Khalandar Basha, N. Madhu
PDF
124-130