Digital signal processing circuits for biomedical monitoring, wireless communication, and machine-learning hardware require high speed, low power consumption, and fault tolerance. This work proposes a high-speed, power-efficient, and fault-tolerant finite impulse response (FIR) filter architecture by integrating Vedic mathematics, reversible logic, and errorcorrection coding into an FPGA-based framework for machine-learning accelerators. A 16-tap FIR filter is implemented on a Xilinx Virtex-5 FPGA using the Urdhva-Tiryakbhayam Vedic multiplication technique with reversible Peres and controlled-NOT (CNOT) gates and a reversible lookahead carry adder (LACA), enabling parallel computation with reduced information loss. A Hamming-code-based error correction code (ECC) module is incorporated to detect and correct single-bit soft errors without the hardware overhead associated with triple modular redundancy (TMR). Synthesis results demonstrate a propagation delay of 30.932 ns and power consumption of 2.645 mW, achieving a 5.57% latency improvement over an multiple constant multiplication (MCM)-based FIR baseline while providing single-bit fault correction. The proposed architecture demonstrates its suitability as a replacement for multiply-accumulate (MAC) units in convolutional neural network accelerators, particularly for powerconstrained and fault-sensitive edge artificial intelligence applications.
