AI-assisted performance prediction and optimization of CMOS and GDI logic circuits at 45 nm

Abstract

An AI-assisted optimization framework is presented for low-power digital circuit design using gate diffusion input (GDI) logic in 45 nm complementary metal oxide semiconductor (CMOS) technology. Core combinational and sequential building blocks, including logic gates, adders, multiplexers, and flip-flops, are implemented at the transistor level using Cadence Virtuoso and compared against conventional CMOS realizations. To accelerate design space exploration, a random forest regression (RFR) model is trained using transistor-level simulation data to predict power consumption and propagation delay based on supply voltage, transistor sizing, and load capacitance. The proposed model achieves prediction accuracy exceeding 95%, reducing repeated SPICE simulation effort by approximately 45%. Simulation results demonstrate that GDI-based designs achieve up to 55% reduction in power consumption, 45% reduction in silicon area, and nearly 50% improvement in power delay product (PDP) compared to CMOS implementations, while maintaining delay variation within acceptable limits. A cross-technology comparison with 90 nm designs further confirms the scalability and energy efficiency of the proposed approach. The integrated artificial intelligence (AI)–GDI method provides an effective solution for energy-efficient very large scale integration (VLSI) and embedded system applications.