Portable verification IP: a UVM-based approach for reusable verification environments in complex IP and SoC verification

Abstract

Reusable and portable verification techniques are becoming more and more necessary due to the growing complexity of system-on-chip (SoC) designs and the need for quick time-to-market. In order to facilitate cross-project reusability, automation, and scalability in SoC verification, this paper introduces a portable verification IP (PVIP) framework based on the universal verification methodology (UVM). The suggested framework improves coverage efficiency and verification portability across heterogeneous platforms by integrating UVM with the portable stimulus standard (PSS). In comparison to traditional UVM-based methods, experimental evaluation shows that the PVIP framework achieves 92% functional coverage, enhances reusability by 87%, and shortens verification cycle time by 27%. These findings demonstrate how PVIP can greatly speed up verification closure, minimize engineering effort, and assist in the development of the next generation of intelligent, scalable, and industry-ready SoC verification environments.