Design of medium grain integrated clock gater for low power clock network

Abstract

The very large scale integration (VLSI) applications were mainly dependent on area, reliability, and cost rather than power. The power-increasing demand was mainly due to the latest growth of electronic products such as portable mobile phones, laptops, and other devices that needs high speed and low power consumption. The power analysis provides insights on the switching activity of various sequential logic and thus would help early power optimization approaches to be incorporated in the design flow. The medium grain integrated clock gater insertion will help with synthesis flows for other low-power techniques to be applied. The power analysis is performed with a physically driven synthesis network for both leakage and dynamic. The power analysis revealed that medium grain clock gaters help with finer granularity of the clock gating principle thus improving gating efficiency. The medium grain clock gating techniques help the tool understand the activities of various sinks thus helping in the insertion of fine gaters as well. For a single medium grain clock gater, the power savings obtained were 41.37% and 79.35% without and with fine gater insertion respectively while cloning of the medium gaters resulted in 45.1% and 67.4% power savings without and with fine gater insertion respectively. The fine-grain integrated clock gating insertion incurred a maximum of 14.7% increased gate count.