Performance analysis of parallel prefix adders developed with field programmable gate array technology

Abstract

In many digital systems like high-performance computing and digital signal processing, parallel prefix adders are vital. Field programmable gate array (FPGA) technology is a well-known platform for developing parallel prefix adders. FPGA performance depends on bit size of the adder, the adder structure chosen, and the implementation specifications. An examination of the performance and area of parallel prefix adders developed using FPGA technology is presented in this research work. We look into how different design factors, such as the adder structure and the number of input bits, affect the performance and area of parallel prefix adders. The different adders used are Sklansky, Kogge-Stone, Brent-Kung, Han-Carlson, and Ladner-Fisher adders. These adders are implemented using Verilog hardware description language (Verilog HDL) on FPGA boards. The performance is significantly influenced by choice of adder structure and design factors optimized for area or performance. The suggestions for choosing the best adder structure and design factors for the best performance or optimized area are obtained from the synthesis results. Ladner-Fisher adders is best parallel prefix adder with respect area and performance compared with the Sklansky, Kogge-Stone, Brent-Kung and Han-Carlson. Our synthesis can be used as a guide for designers looking to construct specific hardware on FPGA.