Design and Implementation of 8x8 Multiplier using 4-2 Compressor and 5-2 Compressor

Abstract

In this paper, a 8x8 multiplier is realized by using 4-2 and 5-2 compressors. Low-power high speed 4-2 compressors and 5-2 compressors are extensively utilized for numerical realizations. Both the compressors circuits that is the 4-2 compressor circuit and 5-2 compressor circuit internally consist of the logic gates i.e. the XOR and XNOR gates.  4-2 compressor circuit has been designed uses a brand new partial-product reduction format that consecutively reduces the utmost output new style of number needs less variety of MOSFET’s compared to Wallace Tree Multipliers. The 4-2 compressor used is created from high-speed and consists of logic gates XOR and XNOR gates and transmission gate primarily based electronic device. The regular delay and switching energy also called as power-delay product (PDP) is differentiated with the 5-2 compressor enforced with 4-2 Compressors and while not compressors, and is evidenced to own minimum delay and PDP. Simulations are performed by mistreatment Xilinx ten.1 ISE.