Low Power VLSI Design and Implementation of Area-Optimized 256-bit AEStandard for Real Time Images on Vertex 5

Abstract

A new Vertex6-chipscope based implementation scheme of the AES-256 (Advanced Encryption Standard, with 256-bit key) encryption and decryption algorithm is proposed in this paper. For maintaining the speed of encryption and decryption, the pipelining technology is applied and the mode of data transmission is modified in this design so that the chip size can be reduced. The 256-bit plaintext and the 256- bit initial key, as well as the 256-bit output of cipher-text, are all divided into four 32-bit consecutive units respectively controlled by the clock. In this novel work, substantial improvement in performance in terms of area, power and dynamic speed has been obtained.