Vol 10, No 3

November 2021

DOI: http://doi.org/10.11591/ijres.v10.i3

Table of Contents

Heuristic algorithms for dynamic scheduling of moldable tasks in multicore embedded systems
Takuma Hikida, Hiroki Nishikawa, Hiroyuki Tomiyama
PDF
157-167
Digital brain: Model-based framework for dependable electroencephalogram sensing and actuation in internet of things system
R. J. Kavitha, Saravanan K. K.
PDF
168-175
ACCESS - IoT enabled smart lock
Harshith Gadupu, Osa Mokharji, Raunak Kankaria, Shrey Kumar, Kayalvizhi Jayavel
PDF
176-185
Neural net implementation of steam properties on FPGA
R. V. S. Krishna Dutt, R. Ganesh, P. Premchand
PDF
186-194
FPGA based co-design of a speed fuzzy logic controller applied to an autonomous car
Emna Aridhi, Decebal Popescu, Abdelkader Mami
PDF
195-211
Enhanced MAC controller architecture for 2D processing based on FPGA with configurable resource allocation
Chiranjeevi G. N., Subhash Kulkarni
PDF
212-220
A low power comparator utilizing MTSCStack, DTTS, and bulk-driven techniques
Mohd Tafir Mustaffa
PDF
221-229
Image processing using a reconfigurable platform: Pre-processing block hardware architecture
Chiranjeevi G. N., Subhash Kulkarni
PDF
230-236
SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
Matias Javier Oliva, Pablo Andrés García, Enrique Mario Spinelli, Alejandro Luis Veiga
PDF
237-248