Vol 7, No 3

November 2018

DOI: http://doi.org/10.11591/ijres.v7.i3

Table of Contents

An Optimal Design of CMOS Two Stage Comparator Circuit using Swarm Intelligence Technique
Sasikumar Sasikumar, Muthaiah Muthaiah
Total views : 109 times
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125-131
Real time FPGA Implementation of PWM Chopper Fed Capacitor Run Induction Motor
N. Murali, V. Balaji
Total views : 76 times
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132-142
Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology
T. Kanthi, D. Sharath Babu Rao
Total views : 76 times
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143-150
High Speed Area Efficient FPGA Implementation of AES Algorithm
P. B. Mane, A. O. Mulani
Total views : 64 times
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151-159
Design Considerations of Reconfigurable CMOS Mixers for Multi-Standard Communication Receiver Systems
Manoj Kumar Vishnoi, Satya Sai Srikant
Total views : 64 times
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160-166
Design and Implementation of a New Architecture of a Real-Time Reconfigurable Digital Modulator (DM) Into QPSK, 8-PSK, and 16-PSK on FPGA
Walder Andre, Olivier Couillard
Total views : 75 times
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167-179
Design and Implementation of LCG-Trivium Key Stream Generator into FPGA
Tchahou Tchendjeu A. E, Tchitnga Robert, Fotsin Hilaire B
Total views : 67 times
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180-188
New Optimized Reconfigurable ALU Design Based on DG-CNTFET Nanotechnology
Houda Ghabri, Dalenda Ben Issa, Hekmet Samet
Total views : 90 times
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189-196
Energy and Area Effective Hardware Design of Lifting Approach Discrete Wavelet Transform
Khamees Khalaf Hasan, Ibrahim Khalil Salih, Abdumuttalib. A. Hussen
Total views : 93 times
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197-206