The IEEE 754 floating-point standard has been the backbone of scientific computing for decades. However, the rapid growth of deep learning (DL) and edge computing has highlighted its drawbacks, mainly in high memory bandwidth and energy usage. To solve this, the posit number system was introduced in 2017. It uses "tapered precision" to dynamically allocate more bits to the "Golden Zone," where artificial intelligence (AI) weights usually fall. Although theoretically better, early posit hardware faced a major "hardware tax" because decoding variable-length regime bits was too slow. This paper presents a detailed survey of posit hardware architectures from 2017 to 2025. We trace its evolution from basic scalar generators to advanced vectorized accelerators and compute-in-memory (CIM) designs. We highlight major improvements, such as leading difference detectors (LDD) and Radix-4 Dividers, which have successfully reduced decoding delay by over 40% and energy consumption by 80%. Our comparative study shows that 16-bit posits can effectively replace 32-bit IEEE floats for memory-bound tasks. It saves 50% memory bandwidth without losing accuracy in applications like ResNet inference and climate modeling. Finally, we conclude that with recent RISC-V posit vector units (PVUs), posits demonstrate competitive potential relative to BFLOAT16 and FP8 formats, particularly in memory-bound edge applications.
