Gauge influence of application mapping algorithms on NoC embedded applications with respect to energy and latency

Abstract

To satisfy efficient requirements of real time embedded applications, high speed communication platforms are needed in multicore system on chip (SoC) architectures and network on chip (NoC) proves promising packet switched interconnection solution. These applications can be either compute, communication or memory sensitive. This paper analyzes application mapping techniques near optimal mapping (NMAP), branch and bound (BB), particle swarm optimization (PSO), gaussian fusion/flow/field (GFF), and random to identify the most appropriate mapping technique for specific application considering tradeoff between latency and energy. For this, machine learning (ML) model has been evaluated on dataset generated from the simulator with 12 different applications. For compute sensitive applications NMAP and PSO, for communication sensitive applications BB and for memory sensitive applications GFF are appropriate mapping algorithms. Also, by varying buffer size it has been noted that for example MWD application with BB mapping algorithm, when buffer size is increased from 2 flits to 4,8,16 flits, latency is reduced by 58.84%, 75%, and 99%, respectively. In contrast, a router with 4 flits/buffer uses nearly the same amount of energy as router with 2 flits/buffer, and routers with 8 flits/buffer and 16 flits/buffer use 11.5% and 66% more energy, respectively. This analysis may benefit researchers conducting further research on the embedded application