SPARTAN– FPGA Implementation for Analog Waveforms Generation by DDS - Direct Digital Synthesis

Abstract

In the last thirty years, low power Field Programmable Gate Arrays (FPGAs) becoming more commonly used to implement a countless of applications in different electronics industry domains. Due to their flexible design, strong compatibility, parallel computing, and compared to the CPU architecture, FPGA accentuate computing efficiency and considered as one of the devices with the lowest application risk and the shortest development cycle among the variety of available programmable circuits families. This paper presents an experimental FPGA implementation of precise analog waveforms generation using the Direct Digital Synthesis (DDS) method based on LookUp Table (LUT) by VHDL dataflow language based ROM designed using embedded RAM of a Xilinx AMD SPARTAN 6 XC6SLX9/CSG324 FPGA Development Board. To provide ROM addresses for reading the stored sample values from the LUT we use a VHDL based counter, and these sample values are converted into a continuous analog waveforms using a Digital to Analog Converter (DAC). To integrate VHDL code into our FPGA chip we use Vivado Design Suite which is a software for synthesis and analysis VHDL designs, and we will visualize the waveform by Vivado test bench which is a proper VHDL source file used to drive simulations