Hardware design for fast gate bootstrapping in fully homomorphic encryption over the Torus

Abstract

Fully homomorphic encryption (FHE) is a promising solution for privacy preserving computations, as it enables operations on encrypted data. Despite its potential, FHE is associated with high computational costs. As the theoretical foundations of FHE mature, mounting interest is focused towards hardware acceleration of established FHE schemes. In this work, we present a hardware implementation of the fast Fourier transform (FFT) tailored for polynomial multiplication and aimed at accelerating gate bootstrapping in Torus fully homomorphic encryption (TFHE) schemes. Our study includes an extensive design-space exploration at various implementation levels, leveraging parallel streaming data to reduce computational latency. We introduce a new algorithm to expedite modular polynomial multiplication using negative wrapped convolution. Our implementation, conducted on reconfigurable hardware, adheres to the default TFHE parameters with 1024-degree polynomials. The results demonstrate a significant performance enhancement, with improvements of up to 30-fold, depending on the FFT design parameters. Our work contributes to the ongoing efforts to optimize FHE, paving the way for more efficient and secure computations.