Exploring the landscape of approximate subtraction methods in ASIC platform

Abstract

Approximate computing has emerged as a crucial technique in modern computing, offering significant benefits for error-resilient applications. Error resilient applications include signal, image, audio processing, and multimedia. These applications will accept the errored results with some degree of tolerance. This approach allows these applications to process and embrace data that may deviate slightly from perfect accuracy. The utility of approximate computing extends to both hardware and software domains. In hardware, arithmetic units are particularly important, among that approximate subtractors have gained attention for their role in these units. A comparative study was conducted on various approximate subtractors from existing literature, considering structural analysis in all scenarios. These approximate subtractors are coded in Verilog hardware description language (HDL) and synthesized in Synopsys electronic design automation (EDA) Tool using Taiwan Semiconductor Manufacturing Company (TSMC) 65 nm technology. Out of the available choices, approximate subtractor 3 is particularly well-suited for processing higher bit data due to its reduced hardware complexity and minimal error. Notably, it outperforms exact subtractors by achieving a notable reduction of 20% in the area delay product (ADP) and 15% in the power delay product (PDP) as process innovation. These improvements highlight the efficiency and effectiveness of approximate subtractor 3, making it a compelling option for various computing applications which accept the inaccurate results.