Side channel power analysis resistance evaluation of masked adders on FPGA

Yilin Zhao, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama

Abstract


Since many internet of things (IoT) devices are threatened by side-channel attacks, security measures are essential for their safe use. However, there are a variety of IoT devices, so the accuracy required depends on the system’s application. In addition, security related to arithmetic operations has been attracting attention in recent years. Therefore, this paper presents an empirical experiment of masking for adders on field programmable gate arrays (FPGAs) and explores the trade-off between cost and security by varying the bit length of the mask. The experimental results show that masking improves power analysis attack resistance, and increasing the bit length of the random numbers used for masking increases security. In particular, the series-connected masked adder is found to be effective in improving power analysis attack resistance.

Keywords


Adders; FPGA; Masking; Power analysis attack; Side channel attacks; T-test; Xilinx

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DOI: http://doi.org/10.11591/ijres.v12.i1.pp97-112

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