Side channel power analysis resistance evaluation of masked adders on FPGA

Yilin Zhao, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama


Since many internet of things (IoT) devices are threatened by side-channel attacks, security measures are essential for their safe use. However, there are a variety of IoT devices, so the accuracy required depends on the system’s application. In addition, security related to arithmetic operations has been attracting attention in recent years. Therefore, this paper presents an empirical experiment of masking for adders on field programmable gate arrays (FPGAs) and explores the trade-off between cost and security by varying the bit length of the mask. The experimental results show that masking improves power analysis attack resistance, and increasing the bit length of the random numbers used for masking increases security. In particular, the series-connected masked adder is found to be effective in improving power analysis attack resistance.


Adders; FPGA; Masking; Power analysis attack; Side channel attacks; T-test; Xilinx

Full Text:




  • There are currently no refbacks.

Creative Commons License
This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

International Journal of Reconfigurable and Embedded Systems (IJRES)
p-ISSN 2089-4864, e-ISSN 2722-2608
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).

Web Analytics Made Easy - Statcounter View IJRES Stats