Role of tuning techniques in advancing the performance of negative capacitance field effecting based full adder

Ravuri Daniel, Bode Prasad, Abhay Chaturvedi, Chinthaguntla Balaswamy, Dorababu Sudarsa, Nallathambi Vinodhkumar, Ramakrishna Reddy Eamani, Ambarapu Sudhakar, Bodapati Venkata Rajanna


The increasing demand for faster, robust, and efficient device development of enabling technology to mass production of industrial research in circuit design deals with challenges like size, efficiency, power, and scalability. This paper, presents a design and analysis of low power high speed full adder using negative capacitance field effecting transistors. A comprehensive study is performed with adiabatic logic and reversable logic. The performance of full adder is studied with metal oxide field effect transistor (MOSFET) and negative capacitance field effecting (NCFET). The NCFET based full adder offers a low power and high speed compared with conventional MOSFET. The complete design and analysis are performed using cadence virtuoso. The adiabatic logic offering low delay of 0.023 ns and reversable logic is offering low power of 7.19 mw.


Adiabatic logic; Full adder; MOSFET; NCFET; Reversible logic

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International Journal of Reconfigurable and Embedded Systems (IJRES)
p-ISSN 2089-4864, e-ISSN 2722-2608
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).

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