Reconfigurable linear feedback shift register for wireless communication and coding

Aakanksha Devrari, Adesh Kumar


Linear feedback shift register (LFSR) is the basic building block of the communication system used in different coding, error detection and correction codes, such as gold, low-density parity check (LDPC), polar, and turbo codes. There are simple shift register-based n-bit counters with a few XOR gates that behave pseudo-randomly. The LFSR is used in chip hardware for high-speed operations, error control, and the generation of pseudo-random numbers. The hardware chip design and performance estimation of the LFSR is the problem for specific communication system. The motivation of the work is to generate the Gold code sequence by the integration of two LFSR. The article proposes the hardware chip design and simulation of two 5-bit LFSR modules used for the gold sequence generator applicable for the communication systems. The novelty of the work is that the design is scalable and can be extended based on the requirements of the systems which is synthesized and experimentally verified on the Zynq-7000 field programmable gate array (FPGA) board. The concept of this design is programmable and can be extended to n-bit based on the applications. The work is supported, and formulated using very high speed integrated circuit hardware description language (VHDL) programming in Xilinx ISE 14.7 software.


Gold sequence; Linear feedback shift register; VHDL; Wireless communication; Xilinx simulation

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International Journal of Reconfigurable and Embedded Systems (IJRES)
p-ISSN 2089-4864, e-ISSN 2722-2608
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).

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