An FPGA application of home security code using verilog

Zaim Zakwan Aminuddin, Irni Hamiza binti Hamzah, Ahmad Asri Abd Samat, Mohaiyedin Idris, Alhan Farhanah Abd Rahim, Zainal Hisham Che Soh

Abstract


Traditional entrance keys performed a number of drawbacks, including the ease with which they can be stolen, duplicated, or misplaced, allowing unauthorized people to gain access to cash, valuables, and other important documents. As known, most digital electronic entrance locks use application specific integrated circuits (ASICs) as based, which have the disadvantage of being unable to be reconfigured, as opposed to field programmable gate arrays (FPGA). This project proposed a home security code lock using verilog hardware descriptive language (HDL) with two unlocking modes, using a button or a keypad which can be changed using a switch. The 7-segment on the Altera DE2-115 trainer board is used to display the passcode press by the keypad. The result of simulation on the keypad using finite state machine (FSM) technique was fulfill the theoretical concept in which it will go to the next state each time the correct input or passcode was entered. When the wrong input or passcode was entered, it will be entered to reset mode. As the conclusion, a fully comply output according to the theoretical FSM concept is fully achieved in this project.

Keywords


Field programmable gate arrays; Finite state machine; ModelSim; Quartus II; Verilog

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DOI: http://doi.org/10.11591/ijres.v11.i3.pp205-214

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