Successive cancellation decoding of polar codes using new hybrid processing element

Sujanth Roy James, Lakshminarayanan Gopalakrishnan


Polar codes are one of the best linear block codes that are capacity achieving and incorporating along with it a simplified encoding and decoding routines. Successive cancellation (SC) algorithm is one of the predominantly used decoding algorithms due to its low complexity. It has broad scopes for hardware architecture design and reformulation. For polar code, the trade-off among the long latency and the silicon area of the SC algorithm is a bottleneck for the design of a high throughput polar decoder. The available prior SC polar decoder designs have higher area requirements for higher block length. This paper introduces a unique reformulation of the processing element (PE) block of SC decoding. The proposed reformulation leads to two benefits: firstly, critical path and hardware complexity of the PE are meaningfully reduced by using a unified adder block. Secondly, the silicon area requirement and the power consumption were also reduced considerably without any loss in performance. The proposed PE is used to build the decoder for various block lengths. Moreover, a Gate-level analysis of the proposed decoder has revealed that the design attains an 18% area reduction and 38% reduction in power consumption over the conventional one with similar performance.


ASIC; Channel coding; Decoder; FPGA architecture; Polar code; Successive cancellation

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International Journal of Reconfigurable and Embedded Systems (IJRES)
p-ISSN 2089-4864, e-ISSN 2722-2608
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