Implementation of Low Power Pipelined 64-bit RISC Processor with Unbiased FPU on CPLD

J. Vijay Kumar, B. Naga Raju, M. Vasu Babu, T. Ramanjappa

Abstract


This article represents the implementation of low power pipelined 64-bit RISC processor on Altera MAXV CPLD device.  The design is verified for arithmetic operations of both fixed and floating point numbers, branch and logical function of RISC processor. For all the jump instruction, the processor architecture will automatically flush the data in the pipeline, so as to avoid any misbehavior. This processor contains FPU unit, which supports double precision IEEE-754 format operations very accurately. The simulation results have been verified by using ModelSim software. The ALU operations and double precision floating point arithmetic operation results are displayed on 7-Segments. The necessary code is written in Verilog HDL.

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DOI: http://doi.org/10.11591/ijres.v5.i2.pp115-120

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