Vol 7, No 2

July 2018

DOI: http://doi.org/10.11591/ijres.v7.i2

Table of Contents

Notice of Retraction Designing of Vedic Based Modulo Multiplication in Residue Number System
Shamim Akhter, Divya Bareja, Satyendra Kumar
Total views : 325 times
Berger Code Based Concurrent Online Self-Testing of Embedded Processors
G. Prasad Acharya, M. Asha Rani
Total views : 227 times
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67-74
FPGA Implementation of DTCWT and PCA Based Watermarking Technique
M. S. Sudha, T. C. Thanuja
Total views : 153 times
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75-83
Impacts of Embedded Generation on Distribution Network Behavior
Puladasu Sudhakar, Sushama Malaji, B. Sarvesh
Total views : 180 times
PDF
84-96
A Power Efficient Self Biased OTA Design Based on g_m/I_D Methodology with Considering Load Variation, Temperature Variation and Power Supply Variation
Vikas Mittal
Total views : 201 times
PDF
97-108
Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders
Nehru.K K, Nagarjuna T, Somanaidu U
Total views : 104 times
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109-117
A Novel Face Recognition Algorithm Using Gabor - based KPCA
Umasankar Ch, D. Naresh Kumar, Md. Abdul Rawoof, D. Khalandar Basha, N. Madhu
Total views : 101 times
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118-124