Neuronal logic gates realization using CSD algorithm

Lakshmi kiran Mukkara, K.Venkata Ramanaiah


Any digital circuit is made with fundamental building blocks i.e. logic gates. Artificial neural networks (ANN) became an emerging area in various applications such as prediction problems, pattern recognition, and robotics and system identification due to its processing capabilities with parallel architecture. Realization of Boolean logic with neural networks is referred as neuronal logic. ANN computes faster as it requires of low and simple precision computations. Also, it requires economic and low precision hardware. Neural network contains more number of addition and multiplication processes. It is known that CSD algorithm computes faster than conventional or standard multipliers. In this paper, VLSI implementation of neuronal half adder with CSD algorithm is proposed and implemented in FPGA. The results are compared with that of conventional and vedic multiplier. It is observed that CSD algorithm provides lowest delay and low power consumption in comparison with vedic algorithm and conventional method but at the expense of minimum area.


CSD (Canonic signed digit); FPGA (Field programmable gate array); VLSI (Very large-scale integrated circuit)

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