An FPGA Implementation of On Chip UART Testing with BIST Techniques

P Bala Gopal, K Hari Kishore

Abstract


A Universal Asynchronous Receiver Transmitter (UART) is usually implemented for asynchronous serial communication, mostly used for short distance communications. It allows full duplex serial communication link and is used in data communication and control system. Nowadays there is a requirement for on chip testing to overcome the product failures. This paper targets the introduction of Built-in self test (BIST) for UART to overcome the above two constraints of testability and data integrity. The 8-bit UART with BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and implemented on SPARTAN 3E FPGA. Results indicate that this model eliminates the need for expensive testers and thereby it can reduce the development time and cost.

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DOI: http://doi.org/10.11591/ijres.v5.i3.pp176-182
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Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.