Effect of integrated power and clock networks on combinational circuits

Rajeshwari Bhat, Mohammad Rashid Ansari, Ruqaiya Khanam


Reduction of power consumption is necessary in a system on chip. To achieve this, power and clock networks can be integrated. This leads to a significant reduction in power consumption in a circuit. This paper explores the effect of such a network on various combinational circuits and compares the power consumption of these circuits with conventional combinational circuits. The combinational circuits which are powered by the proposed circuit consume lesser power as compared to conventional combinational circuits.


Clock network; Combinational circuits; Gates; Inverter; Power efficiency; Sequential circuits

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DOI: http://doi.org/10.11591/ijres.v9.i3.pp242-248
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