6 Transistors and 1 memristor based memory cell

Kazi Fatima Sharif, Satyendra N. Biswas


Area efficient and stable memory design is one of the most important tasks in designing system on chip. This research concentrates in designing a new type of hybrid memory model by using only nMOS transistors and memristor. The proposed memory cell is very stable during successive read operates and comparatively faster and also occupies less amount of silicon area. The stability of the data during successive read operation and noise margin are in the promising range. Extensive simulation results using LTspice and Cadence software tools demonstrate the validity and competency of the proposed model.


Memory cell; nMOS; SRAM; Successive read; Static noise margin

Full Text:


DOI: http://doi.org/10.11591/ijres.v9.i1.pp42-51


  • There are currently no refbacks.

Creative Commons License
This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

View IJRES Stats