Pandeshwara, Prakash Tunga, RNS Institute of Technology, India

• Vol 14, No 1: March 2025 - VLSI Design
  Design of medium grain integrated clock gater for low power clock network
  Abstract  PDF

International Journal of Reconfigurable and Embedded Systems (IJRES)
p-ISSN 2089-4864, e-ISSN 2722-2608
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).

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