IJRES Citedness in Scopus

International Journal of Reconfigurable and Embedded Systems (IJRES)
Citedness in Scopus: 115 times (from 54 documents)
Source: Scopus (Export Date: Aug 8, 2021)


Goud, V., Padmaja, V. Vehicle accident automatic detection and remote alarm device. (2012) International Journal of Reconfigurable and Embedded Systems (IJRES), 1 (2), pp. 49-54. Cited 19 times.

El Adib, S., Raissouni, N. AES Encryption Algorithm Hardware Implementation: Throughput and Area Comparison of 128, 192 and 256-bits Key. (2012) International Journal of Reconfigurable and Embedded Systems (IJRES), 1 (2), pp. 67-74. Cited 15 times.

Nayyar, A. An Encyclopedia Coverage of Compiler’s, Programmer’s & Simulator’s for 8051, PIC, AVR, ARM, Arduino Embedded Technologies. (2016) International Journal of Reconfigurable and Embedded Systems (IJRES), 5 (1), pp. 18-41. Cited 10 times.

Sutikno, T., Jidin, A.Z., Jidin, A., Idris, N.R.N. Simplified VHDL coding of modified non-restoring square root calculator. (2012) International Journal of Reconfigurable and Embedded Systems., 1 (1), pp. 37-42. Cited 9 times.

Saravanan, M., Nandakumar, R., Veerabalaji, G. Effectual SVPWM Techniques and Implementation of FPGA Based Induction Motor Drive. (2012) International Journal of Reconfigurable and Embedded Systems, 1 (1), pp. 11-18. Cited 7 times.

Kulkarni, R.N., Bhaskar, P.C. Decision based median filter algorithm using resource optimized FPGA to extract impulse noise. (2014) International Journal of Reconfigurable and Embedded Systems, 3 (1), pp. 18-22. Cited 6 times.

Dilip, P.A., Rameshbabu, K., Ashok, K.P., Shivdas, S.A. Bilinear interpolation image scaling processor for VLSI architecure. (2014) International Journal of Reconfigurable and Embedded Systems, 3 (3), pp. 104-113. Cited 6 times.

Bhople, S.S., Gaikwad, M.A. Design of Mesh and Torus Topologies for Network-On-Chip Application. (2013) International Journal of Reconfigurable and Embedded Systems, 2 (2), pp. 76-82. Cited 6 times.

Beldachi, A.F., Hosseinabady, M., Nunez-Yanez, J.L. Configurable Router Design for Dynamically Reconfigurable Systems based on the socwire noc. (2013) International Journal of Reconfigurable and Embedded Systems (IJRES), 2 (1), pp. 27-48. Cited 5 times.

Sutikno, T., Idris, N.R.N., Widodo, N.S., Jidin, A. Fpga based a PWM technique for permanent magnet ac motor drives. (2012) International Journal of Reconfigurable and Embedded Systems, 1 (2), pp. 43-48. Cited 5 times.

Hussain, Md. Z., Parvin, K. N. Low power and high performance FFT with different radices. (2019) International Journal of Reconfigurable and Embedded Systems (IJRES), 8 (2), pp. 99-106. Cited 4 times.

Mano, R., Kishore Raja, P.C., Joseph, C., Baskar, R. Hardware Implementation of Intrusion Detection System for Ad-Hoc Network. (2016) International Journal of Reconfigurable and Embedded Systems (IJRES), 5 (3), pp. 153-159. Cited 3 times.

Yusof, N.M., Jidin, A.Z., Sze, L.M. Web based home security, automation system. (2016) International Journal of Reconfigurable and Embedded Systems IJRES, 5 (2), pp. 92-98. Cited 3 times.

Dessai, S., Mahir, M.M., Mayur, R., Singha, N., Avaradhi, V. Design and development of low cost navigation and security system for Indian fisherman using adrino nano platform. (2015) International Journal of Reconfigurable and Embedded Systems, 4 (1), pp. 28-41. Cited 3 times.

Hasan, M.Y., Poornima, V.P., Sujendran, S., Karthikraja, D. FPGA Based Firewall using Embedded Processor for Vulnarability Packet Detection. (2014) International Journal of Reconfigurable and Embedded Systems (IJRES), 3 (1), pp. 31-38. Cited 3 times.

Mohammad, I., Ramananjaneyulu, K. FPGA Implementation of a 64-bit RlSC Processor Using VHDL. (2012) Proceedings of International Journal of Reconfigurable and Embedded Systems(IJRES), 1 (2), pp. 59-66. Cited 3 times.

Stacul, A. Filtering and acquisition of serial data frames using xilinx system generator. (2020) International Journal of Reconfigurable and Embedded systems (IJRES), 9, pp. 1-11. Cited 2 times.

Pandia, H., Rangapariya, M., Rajput, J. Implement Embedded Controller Using FPGA. (2019) International Journal of Reconfigurable and Embedded Systems, 8 (2), pp. 130-144. Cited 2 times.

Ghabri, H., Issa, D.B., Samet, H. New Optimized Reconfigurable ALU Design Based on DG-CNTFET Nanotechnology. (2018) International Journal of Reconfigurable and Embedded Systems, 7(3), pp. 195-202. Cited 2 times.

Jadhav, S.B., Mane, N.N. A novel high speed FPGA architecture for fir filter design. (2012) International Journal of Reconfigurable and Embedded Systems (IJRES), 1 (1), pp. 1-10. Cited 2 times.

Bhowmik, A., Karforma, S., Dey, J. Recurrence relation and DNA sequence: A state-of-art technique for secret sharing. (2021) International Journal of Reconfigurable and Embedded Systems (IJRES), 10 (1), pp. 65-76. Cited 1 time.

Aboelela, M. Application of optimal artificial intelligence based tuned controllers to a class of embedded nonlinear power system. (2020) International Journal of Reconfigurable and Embedded Systems (IJRES), 9 (1), pp. 83-92. Cited 1 time.

Rabie, A. Data encryption based on multi-order FRFT, and FPGA implementation of des algorithm. (2020) International Journal of Reconfigurable and Embedded Systems (IJRES), 9 (2), pp. 141-152. Cited 1 time.

Atiqur, R., Li, Y. Automated smart car parking system using raspberry pi 4 and ios application. (2020) International Journal of Reconfigurable and Embedded Systems (IJRES), 9 (3), pp. 229-234. Cited 1 time.

Sharif, K.F., Biswas, S.N. 6 Transistors and 1 memristor based memory cell. (2020) International Journal of Reconfigurable and Embedded Systems, 9 (1), pp. 42-51. Cited 1 time.

Gobimohan, S., Murali, N. Implementation of PWM AC chopper controller for capacitor run induction motor drive via bacterial foraging optimization algorithm. (2020) International Journal of Reconfigurable and Embedded Systems (IJRES), 9 (3), pp. 169-177. Cited 1 time.

Hossain, M., Lee, W. Integration Testing Based on Indirect Interaction for Embedded System. (2019) International Journal of Reconfigurable and Embedded Systems, 8 (2), pp. 86-98. Cited 1 time.

Palanisamy, R., Vejayakumar, K. Switching Pulse Generation for DC-DC Boost Converter Using Xilinx-ISE With FPGA Processor. (2019) International Journal of Reconfigurable and Embedded Systems, 8, pp. 81-85. Cited 1 time.

Tabra, Yasmine M., Sabbar, Bayan Mahdi. FPGA implementation of new LM-SPIHT colored image compression with reduced complexity and low memory requirement compatible for 5G. (2019) International Journal of Reconfigurable and Embedded Systems (IJRES), 8 (1), pp. 1-13. Cited 1 time.

Acharya, P., Rani, M. Berger Code Based Concurrent Online Self-Testing of Embedded Processor. (2018) International Journal of Reconfigurable and Embedded Systems, 39 (11), pp. 1-6. Cited 1 time.

Dessai, S., Sandeep, G. Embedded Hardware Circuit and Software Development of USB based Hardware Accelerator. (2018) International Journal of Reconfigurable and Embedded Systems, 7 (1), pp. 21-33. Cited 1 time.

Mane, P. B., Mulani, A. O. High speed area efficient FPGA implementation of AES algorithm. (2018) International Journal of Reconfigurable and Embedded Systems (IJRES), 7 (3), pp. 157-165. Cited 1 time.

Vighnesh, Anil, Rachana, Sharvana, Sanjana, Hegde, Rajeshwari, Nagabhushana, B. Application of Inverse Perspective Mapping for Advanced Driver Assistance Systems in Automotive Embedded Systems. (2018) International Journal of Reconfigurable and Embedded Systems (IJRES), 6 (3), pp. 150-159. Cited 1 time.

Andre, W., Couillard, O. Design and Implementation of a New Architecture of a Real-Time Reconfigurable Digital Modulator (DM) Into QPSK, 8-PSK, and 16-PSK on FPGA. (2018) International Journal of Reconfigurable and Embedded Systems, 7 (3), pp. 173-185. Cited 1 time.

Kanthi, T., Sharath Babu Rao, D. Design and Analysis of CMOS Low Noise Amplifier Circuit for 5-GHz Cascode and Folded Cascode in 180nm Technology. (2018) International Journal of Reconfigurable and Embedded Systems (IJRES), 7 (3), pp. 149-156. Cited 1 time.

Mandalapu, H., Krishna, B.M. FPGA Implementation of DS-CDMA Transmitter and Receiver. (2017) International Journal of Reconfigurable and Embedded Systems (IJRES), 6 (3), pp. 179-185. Cited 1 time.

Pandya, D. H., Rangapariya, M. M., Rajput, M. J. Implement Embedded Controller using FPGA Chip. (2017) International Journal of Reconfigurable and Embedded Systems, 4 (6), pp. 140-152. Cited 1 time.

Pandey, Shubham, Chandewar, Shubham, Krishnamoorthy, A. Smart assisted vehicle for disabled/elderly using raspberry Pi. (2017) International Journal of Reconfigurable and Embedded Systems (IJRES), 6 (2), pp. 82-87. Cited 1 time.

Pawase, R., Futane, N. P. MEMS seismic sensor with FPAA-based interface circuit for frequency-drift compensation using ANN. (2017) International Journal of Reconfigurable and Embedded Systems (IJRES), 6, pp. 120-126. Cited 1 time.

Raghav, D.B.V., Bandi, S.K. Digitalized electronic voting system. (2016) International Journal of Reconfigurable and Embedded Systems (IJRES), 5, pp. 148-152. Cited 1 time.

Vinayak Pandit, K., Dessai, S., Chaudhari, S. Development of bsp for arm9 evaluation board. (2015) International Journal of Reconfigurable and Embedded Systems IJRES, 4 (3), pp. 161-172. Cited 1 time.

Ru, S., Cu, P., Baby, N., Ru, R. FPGA Synthesis of Reconfigurable Modules for FIR Filter. (2015) International Journal of Reconfigurable and Embedded Systems (IJRES), 4 (2), pp. 63-70. Cited 1 time.

Kannan, C. Nios II based secure test wrapper design for testing cryptographic algorithms. (2015) International Journal of Reconfigurable and Embedded Systems, 4 (3), pp. 185-191. Cited 1 time.

Meena, N., Parihar, N. Real-Time Algorithms and Architectures for several user Channel Detection in Wireless Base Station Receivers.
(2015) International Journal of Reconfigurable and Embedded Systems, 4 (2), p. 82-98. Cited 1 time.

Reddy, N.K., Suresh, N. An efficient approach for design and testing of FPGA programming using labview. (2015) International Journal of Reconfigurable and Embedded Systems (IJRES), 4 (3), p. 192. Cited 1 time.

Bailmare, R.H., Honale, S.J., Kinge, P.V. Design and implementation of adaptive fir filter using systolic architecture. (2014) International Journal of Reconfigurable and Embedded Systems (IJRES), 3 (2), pp. 54-61. Cited 1 time.

Kumar, M., Nadagouda, R.V., Jegan, R. FPGA based multichannel bit error rate tester for spacecraft data acquisition system. (2014) International Journal of Reconfigurable and Embedded Systems (IJRES), 3 (2), pp. 76-84. Cited 1 time.

Manoj Kumar, A., Nadagouda, R.V., Jegan, R. FPGA based Multichannel Bit Error Rate Tester for Spacecraft Data Acquisition System.(2014) International Journal of Reconfigurable and Embedded Systems (IJRES), 3 (2). Cited 1 time.

Anjomshoa, M., Mahani, A. A novel evolutionary method for designing optimized multifunctional logic modules. (2013) International Journal of Reconfigurable and Embedded Systems, 2 (2), pp. 55-60. Cited 1 time.

Patel, J., Suthar, H., Gadit, J. VHDL Implementation of H.264 Video Coding Standard. (2012) International Journal of Reconfigurable and Embedded Systems (IJRES), 1 (3), pp. 95-102. Cited 1 time.

Ashwini, S.D. A novel FPGA based leading one anticipation algorithm for floating point arithmetic units. (2012) International Journal of Reconfigurable and Embedded Systems, 1, pp. 19-24. Cited 1 time.

McDermott, M. QueuedStack Dataflow Processing Element for a Cognitive Sensor Platform. (2012) International Journal of Reconfigurable and Embedded Systems (IJRES), 1 (3), pp. 75-86. Cited 1 time.

Dhekekar, R., Srikanth, N. Digital Control of Static Var Compensator with Field Programmable Gate Array. (2012) International Journal of Reconfigurable and Embedded Systems (IJRES), 1 (3), pp. 87-94. Cited 1 time.

Deshmukh, A.S. A novel FPGA based leading one anticipation algorithm for floating point arithmetic units. (2012) International Journal of Reconfigurable and Embedded systems, 1 (1), pp. 19-24. Cited 1 time.