FPGA in hardware description language based digital clock alarm system with 24-hr format

ABSTRACT


INTRODUCTION
An alarm clock is one of the devices which is very useful in human live.It solved a problem that everyone faces, which is determining the current time and also helping up to wake after sleep using alarm system.With this device, everyone can have a manageable and coordinated life.
Today, technology has progressed to the point where a system may be integrated onto a single chip, a process called as system on chip (SOC) [1], [2].Likewise, this also applies to the digital clock.The system is currently comprised of a microprocessor [2], [3].The problem related to the digital clock with the microprocessor is the performance of processing speed [4], [5] and reprogrammability issue [6], [7].Following the trend of the period, numerous additional features may be incorporated in the future [8].Therefore, it is essential to study the implementation of field programmable gate array (FPGA) in a digital clock [9].Digital clocks use FPGA technology because it has a simpler circuit topology [10], quicker development cycle [11], and faster running speed [12].FPGA is also used to solve the issue regarding on reprogrammability of the system [13].FPGA can be used to solved complicated computational issues which requires increased speed and reprogrammability advantage [14]

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superior to microcontroller or microprocessor since it is favourable in terms of performance and reconfigurable [15], making it easier to enhance the existing system [13].
The objective of this project is to create an hardware description language (HDL)-based digital clock with alarm system and implement it on an FPGA board in order to resolve the issue.To fulfil the objective, a digital clock with alarm system must be designed utilizing the verilog HDL programming language.The system's functionality will then be validated using ModelSim Altera Starter Edition for Quartus Prime 20.1 Lite Edition.It will then be implemented on an FPGA board for verification purposes.This study focuses on a 24-hour clock with an alarm system.This comprised coding, code analysis and synthesis, input and output pin assignments, compilation of the system, and download to the Altera DE2-115 FPGA board.
The main advantage of FPGA is its performance of speed.The high speed of an FPGA is a result of the system's I/O bandwidth to local memory, pipelining, and parallelism features [16], [17].Parallel processing is one of the features that distinguishes FPGA from other processor types [18], [19].FPGA is substantially superior to microcontrollers in terms of speed, I/O count, and performance [20].Rodriguez-Andina et al. [21] stated that internal memory is essential for enhancing processing performance and optimizing I/O pin utilization.In addition, internal memory blocks offer the benefit of constructing complex functions, such as counters and multipliers.While digital clocks can be built using a variety of technologies, FPGAs offer major benefits such as a greater number of I/O ports [17].It is desirable to explore digital clocks using FPGA due to their reduced system usage, increased system reliability, and increased working speed [12], [22] likewise, due to the advantages of a simpler circuit construction and faster operation, explained it is essential to analyze the digital clock using FPGA.
As compared to application-specific integrated circuits (ASICs), FPGAs have simpler design cycle in which means the design tools take care of a major function by themselves, such as placement, routing, and timing in reference to specifications that need to be set [23].Apart from that, although the product has been finalised, built, and delivered, it may be easily updated, adapted, and reprogrammable.FPGAs are ideal for time-critical systems [24] and is the right solution if the application requires constant bug fixes, feature, design changes, and software flexibility.Table 1 summarizes performance of FPGAs to microcontrollers and ASICs across various aspects.
Like any other microcontrollers, FPGA also facing reprogrammable issues in which one of the solutions presented in this paper is to simulate the developed Verilog coding using ModelSim-Altera Starter Edition 13.1 software.The output is presented in timing waveforms.From these generated output waveforms, it can be compared with the expected output.

RESEARCH METHOD
Figure 1 depicts the design of the top module of a digital alarm clock.There are 14 inputs including 50 MHz clock and 8 outputs.The input ports were listed as shown in the following diagram.The inputs for 'Reset' are used to reset all operations to zero.Consequently, the clock time, alarm time, input time, and alarm time switch to zero.While 'clock_50 MHz' is generated from a 50 MHz clock source.The frequency was subsequently decreased to 1 Hz to match the duration of 1 s during clock operation.Load data time (LD_time) is the switch that loads the input time into the clock.While 'LD_alarm' loaded input time into the alarm time.The 'Increment button' is utilized to assign values to inputs.As it is pressed, the time will be increased by 1 unit, depending on which switch is active at the time: switch Hin_1, which corresponds to the most significant hour, or switch Hin_0, which relates to the least significant hour.This was also applied to minutes.The 'ctime' switch is used to display the current time.'atime' is used to display alarm time, whereas 'stime' displays input time.The 'AL_ON' switch activates the alarm system, while the 'STOP_al' switch deactivates it.
Figure 2 shows the overall components of submodule used for this study.It consists the submodules of clock reducer, time input, clock function, clock output, current time, and alarm function.All submodules were tested with their own testbench coding to ensure the functionality of each submodule.In clock reducer, the input of this module is 50 MHz clock and reset.It was then reduced to 1 Hz clock which equivalent to 1 s for operation in time input, clock function, and alarm function.In this module, it uses counter to count for 1 s clock production.If the counter is equal to 25,000,000, the 1 s clock will change in state from high to low.The reason why 25,000,000 count is used as the clock consists of 2 states, high and low.Each will be representing 0.5 s.To make 1 s clock, each state must have the count of 25,000,000 before changing to another state.If the counter reaches its target, it will reset back to zero.In time input, the user need to insert their desired time for clock time or alarm time using 4 switches which H_in1, H_in0, M_in1, and M in0.These switches representing the hour and the minutes, most and least significant digit.Each push of increment_button will increase the input value by 1.The value will reset if it exceeds the maximum pre-set value of clock time.If reset switch is turned on, all input will reset to 0. In clock function, this is where the input from user will be loaded either to clock time or alarm time.If LD time is switched on, the input will be loaded to the clock time.While LD_alarm will load the input into alarm time.This module also where the clock time operates through counters through seconds, hour and minutes.In clock output, the internal clock time know as temporary (tmp) will be converted to 6 types of output for clock time display.It includes most significant and least significant of hours, minutes and seconds.In current time, it utilized 3 types of input which is clock time, alarm time, and setting time.The users can choose to see which type of display they want to see using 3 switches.The switches are 'ctime' which displays current clock time, 'atime' for displaying the alarm time and 'stime' for input time.And all of the input will be assigned to 7 different seven-segment displays.The arrangement of seven-segment display is 7'b (6 5 4 3 2 1 0).Seven segment display is active low meaning than logic low will light up the character of display.While logic high will turn off the character.In alarm function, it will compare the clock time and the alarm time.If both are similar and the switch AL_ON is on, the alarm will be turned on.In this case, the red LED will represent the alarm.If AL_ON is not on, the Alarm will not be turned on.To stop the alarm, user must switch STOP AL_ON.The flowchart of a digital clock with alarm system is depicted in Figure 3.This digital clock has three display modes.The user can choose between the clock, alarm, and set times.If the user selects reset switch, all time modes are reset to 0. If the user does not activate any of the three display switches, the seven-segment display will be blank.With input time mode, the user may also provide input to edit the clock time and alarm time.There are four switches to choose which portion of time is to be modified.Two are the maximum and minimum hours, while the other two are the maximum and minimum minutes.If the user presses the increment button, the value will grow by one.If the value of H_in1 is more than 2, for instance, it will be reset to zero.And it will continue if the button is still pressed.This will facilitate the user's input.If the user activates the LD time switch, the input will be set to clock time.The input will be loaded at alarm time for LD alarm.If AL_ON is enabled, the Alarm will be triggered if the clock time coincides with the alarm time.

RESULTS AND DISCUSSION
In this section, it is divided into 2 categories: software simulation and hardware implementation.In the part of software simulation, ModelSim-Altera Starter Edition 13.1 had been used.Whereby for hardware implementation, Cyclone IV of Altera DE2-115 development and education board had been utilized for verification.

Software simulation
Figures 4 and 5 reflect the timing diagram for the top module of a digital alarm clock.When 'stime' is enabled, the seven-segment displays the time input.In this instance, switch Min0 is activated.If the 'increment button' was pressed, the input will be added to Min_0 by 1.Then, LD alarm is enabled, which loads the input with the alarm time.The current alarm time is 0001 hours.Seven-segment display output HEX0-HEX7 displays three types of display modes.It consists of 7'bit registers, with each of LED of a seven-segment display utilizing a bit of register.7'b describes the configuration of seven-segment display (6 5 4 3 2 1 0).Seven-segment displays are low active type, therefore 0 input will illuminate the display while 1 will turn it off.

Hardware implementation
In this project, the digital clock with alarm system accepts input from 12 switches, a 50 MHz clock, and one push button.While the output is 7 unit of seven-segment display and a red LED.Figures 6, 7

CONCLUSION
In conclusion, the digital clock with alarm system has been successfully implemented into Altera DE2-115 board.It consists of switches and button as input while seven-segment display and red LED as output.This digital clock has 3 types of display which is clock, alarm, and input time.Therefore, this study will improve the current technology of digital clock where with usage of microcontroller or microprocessor having disadvantages in term of performance and reprogrammability issues.

Figure 1 .Figure 2 .
Figure 1.Top module of a digital clock alarm system

Figure 3 .
Figure 3. Flowchart of digital clock alarm system

Figure 4 .Figure 5 .
Figure 4. Timing diagram of time input for alarm time

Figure 6 .Figure 7 .Figure 8 .
Figure 6.Display mode of alarm time on Altera DE2-115 . It is explained that FPGA implementation is FPGA in hardware description language based digital clock … (Mohd Faris Izzwan Mohd Sayudzi)