Role of tuning techniques in advancing the performance of negative capacitance field effecting based full adder

The increasing demand for faster, robust, and efficient device development of enabling technology to mass production of industrial research in circuit design deals with challenges like size, efficiency, power


INTRODUCTION
The modern embedded systems and signal processing processors demand low power and high speed full adder [1].Many researchers have developed versions of complete adders using XOR/XNOR gates and complementary metal-oxide semiconductor (CMOS) inverters [2].The transistor technology and logic utilised to create the complete adder will decide the performance [3].Transistor scaling is vital to building low-power integrated circuit (IC).Transistors technologies as high-electron-mobility transistor (HEMT), heterojunction bipolar transistor (HBT), metal oxide semiconductor field effect transistor (MOSFET), and negative capacitance field effect transistor (NCFET) [4], [5] facilitate scaling to lower levels [6].Other than typical full adder design techniques (using XOR/XNOR (or) CMOS inverters), there are some popular digital logics accessible, i.e., efficient charge recovery logic (ECRL), adiabatic logic, dual rail circuits (DRC), and reversible logic [7], [8].In this paper, we give an examination of the design of a full adder using several transistor technologies and different forms of logic to boost the ability in the elements of delay and power.When compared with the typical XOR operations of full adder cells, adiabatic logic [9], [10] and reversable logic- based full adder cells offer outstanding performance.This paper is organized as follows.Section 2 presents the related work.In section 3, problem statement and the proposed method is described.In section 4, design and analysis is presented.In section 5, described results and analysis.Finally, the main conclusion and future directions are parented in section 6.

RELATED WORK
Consumer electronics and medical devices use ultra-low-power circuitry.Low-power technology powers CMOS scaling.Digital signal processing uses complex techniques like convolution, which requires efficient arithmetic circuits.As arithmetic circuits become more complicated, power consumption becomes more critical.This complicates arithmetic circuits, making energy usage more important.Cell phones, PDAs, and laptops are in high demand because arithmetic circuits use a low-power full adder [11].Table 1 show that the ECRL, DRC, secured quasi-adiabatic logic (SQAL), and one-dimensional capacitor (ODC) have been proposed and studied to understand future energy-efficient high-end computing systems.In arithmetic, addition is a fundamental operation, addition-based operations like subtraction, and multiplication.The full adder is an essential module of the binary adder.Improving the performance of 1-bit full-adder is a top priority that has drawn a lot of research resources [20], [21].Full adder develops highperformance, low-power systems.Scientists have long prioritised full adder MOSFET threshold voltage.
Table 2 shows that channel length (L), channel width (W), and gate and drain voltage MOSFET characteristics determine drain current.
The Boltzmann tyranny limits typical MOSFET subthreshold swing to 60 mV/decade at normal temperature, making it difficult to lower supply voltage and power usage [22].NCFETs may benefit from future IC nodes [23].Because of its integrated ferroelectric layer in the gate stacks, an NCFET has a larger switching current ratio [24]- [26] and a steeper subthreshold swing than a MOSFET.In devices and circuits, it improves performance while using less power.The ferroelectric material's non-stable NCE requires careful CFE-tounderlying MOSFET capacitance matching for NCFET performance [27].NCFET transistors use a ferroelectric (FE) layer in the transistor gate stack to function at lower VDDs while retaining switching speed [28], [29].The NCFET's threshold voltage, drain current, and device parameters are provided in (3), (4), and Table 3.
The drain current of the NCFET is:

PROBLEM STATEMENT AND DESIGN METHOD
Portable battery-operated systems are moving towards better speeds, smaller on-chip regions, and lower power consumption [30]- [33].Convolution, correlation, filtering, and other efficient arithmetic operations are used in modern microprocessors and digital signal processor (DSP).These operations depend on full adders.Power consumption can be reduced by reducing arithmetic operation energy.Low supply voltage and low-frequency input pulses delay and degrade an arithmetic system's circuits, reducing power consumption.Static and dynamic logic design CMOS full adder cells.Static full adder cells are simpler to develop, more dependable, and consume less power.Several logic topologies created full adder cells.Some topologies perform better than others.Table 4 describes recent real issues.Developing such systems requires full adder cell design with low power consumption and fast speed.Figure 1 illustrates the problem statement using a flowchart.The selection of optimal transistor technology and reduction of leakage currents helps to reduce the circuit power supply.

High speed
The selection of design logic helps to achieve the design of high speed full adder.

Reversable logic
The proposed reversible logic based full adder using MOSFET as shown in Figure 6.In this circuit, there are three inputs (A, B, and Cin) representing the two binary numbers to be added and the carry input, and two outputs (Sum and Cout) representing the sum and carry-out of the addition.A reversible full adder using NCFETs as shown in Figure 7 can be implemented using a combination of reversible gates, such as the Toffoli gate or Fredkin gate.These gates can be constructed using NCFETs, but the actual circuit design and fabrication would require specialized expertise and tools.Figure 8 shows transient response of a NCFET refers to how the transistor behaves during the time it takes to transition from one state to another in response to a change in its input or initial conditions.

RESULTS AND DISCUSSION
In order to design and analyses the simulation of the described full adder circuits, the CADANCE software was used.A MOSFET and an NCFET are used to evaluate the overall adder's performance.MOSFET and NCFET model files used for simulation and design NCFETs perform well in delay and power compared to conventional MOSFETs, as shown in Tables 6 and 7. Respectively of the comprehensive study on adiabatic and reversible logic using 45 nm technology by both MOSFET-and NCFET-based full adder.Figure 9 shows the power consumption of the proposed logic 1 (552 mW) and logic 2 (7.19 mW) are stands out as the most energy-efficient among existing methods.Figure 10 shows delay of the logic 1 (1.68 ns) and logic 2 (0.023 ns) are exceptionally low delay than the existing methods.The primary takeaways from the performance analysis are that the adiabatic logic-based full adder has a fast processing speed, whereas the reversible logic-based full adder has low overall power consumption.

CONCLUSION
NCFETs outperform MOSFETs.Reversible and adiabatic logic evaluated NCFET based complete adder performance.The performance investigation found that the adiabatic logic-based full adder is fast and the reversible logic-based one is low-power.Low-power, high-speed embedded system IC design prefers the given full adder.The choice of NCFET-based full adder, one designed using adiabatic logic and the other using reversible logic, appears to be well-suited for the needs of low-power, high-speed embedded system ICs.NCFET technology's novelty presents fabrication problems that must be overcome to seamlessly incorporate it into semiconductor processes, requiring further research for scalability and cost-effectiveness.Adiabatic and reversible logic architectures have larger circuit sizes than CMOS-based designs, which may limit spaceconstrained applications.These constraints highlight the need for continual research and innovation to overcome them and maximize NCFET technology's potential.[32] [33] NCFET-based full adder designs have several promising futures.First, more reliable and costeffective fabrication methods are essential to this technology's applicability for mass production.Hybrid logic architectures that combine adiabatic and reversible logic may balance power efficiency and speed, reducing area overhead.To ensure performance under varied environmental circumstances, research should also improve temperature resilience.Integration of NCFET-based designs with legacy systems should also be a priority to ease the transition.Finally, customizing complete adder designs for low-power, high-speed embedded system applications can improve performance and energy efficiency.These future efforts aim to maximize NCFET-based designs' practical uses.

Table 1 .
Full adder design state of art [19]abatic" thermodynamic processes do not exchange energy with the outside world; hence no power or energy is lost.This logic decreases power dissipation when switching.It recycles energy from the load capacitance for the following action.[19]Finfield-effect transistor (FinFET) CMOS-36 11 11 Many computational circuits use full adders.This study uses graphene-dielectric-metal waveguide tuning to create a compact, efficient electro-optical full adder.

Table 2 .
MOSFET properties Role of tuning techniques in advancing the performance of negative capacitance field … (Ravuri Daniel)

Table 4 .
Problem statement

Table 6 .
Comprehensive study on adiabatic and reversable logic

Table 7 .
Work comparison with literature