O. Mulani, A., AISSMS Inst. Of Information Technology, India

• Vol 7, No 3: November 2018 - Other articles
  High Speed Area Efficient FPGA Implementation of AES Algorithm
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International Journal of Reconfigurable and Embedded Systems (IJRES)
p-ISSN 2089-4864, e-ISSN 2722-2608
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).