A system verilog approach for verification of memory controller

Sowmya K B, Gagana P

Abstract


Memory performance has become the major bottleneck to improve the overall performance of the computer system. By using memory controller, there is effective control of data between processor and memory. In this paper, a memory controller for interfacing Synchronous Static Random Access Memory (SSRAM), Synchronous Dynamic Random Access Memory (SDRAM), Read Only Memory (ROM) and FLASH which is Electrically Erasable Programmable Read-Only Memory is designed and a coverage driven Constraint random verification environment is built for the designed memory controller. Verification plays an important role in any design flow as it is done before silicon development. It is done at time of product development for quality checking and bug fixing in design.

Keywords


Configuration registers; Coverage report; RAM; ROM; Verification environment; Wishbone interface

Full Text:

PDF

References


Rudolf Usselmann, “Memory Controller IP Core”, Open Cores Revision.1.7 January 21, 2002.

2nd Generation Intel® Core™ Processor Family Desktop, Intel® Pentium® Processor Family Desktop, and Intel® Celeron® Processor Family Desktop Datasheet, Volume 1

Barbara Johnson, “MSC711x Memory Controller Usage Guidelines Supporting Double Data Rate (DDR) SDRAM Devices”, NXP, Revision. 1, 3/2007

K. Khalifa, H. Fawzy, S. El-Ashry, K. Salah, "Memory controller architectures: A comparative study", 8th IEEE Design and Test Symposium, Dec. 2013.

Yingpan Wu, Lixin Yu, Lidong Lan, and Haiyang Zhou: “A Coverage-Driven Constraint Random-Based Functional Verification Method of Memory Controller” in Proc. 19th IEEE/IFIP International Conf. Rapid System Prototyping, pp. 99 – 104, June 2008.

K. Agarwal, V. K. Magraiya and A. K. Saxena, "Verification and Simulation of New Designed NAND Flash Memory Controller”, International Conference on Communication Systems and Network Technologies, Gwalior, 2013, pp. 762-766.

Park Soo Il, Song Jae Yeol, Park Seok Hwi and Jung Ji Hoon, "Design of memory controller Design of general-purpose memory controller," International SoC Design Conference, Busan, 2008, pp. III-39-III-41.

I. Silas, I. Frumkin, E. Hazan, E. Mor, G. Zobin, "System-level validation of the intel pentium M processor", Intel Technol. J., vol. 7, no. 2, pp. 38-43, May 2003.

Shawn Kung, "Native PCIs SSD Controllers Next Generation Enterprise Architecture for Scalable I/O Performance", White Paper Marvell, Jan-2012.

A. Aharon, D. Goodman, M. Levinger et al., "Test Program Generation for Functional Verification of PowerPC processors in IBM", Proc.32th DAC IEEE, pp. 279-285.




DOI: http://doi.org/10.11591/ijres.v9.i2.pp%25p
Total views : 43 times

Refbacks

  • There are currently no refbacks.


View IJRES Stats

Creative Commons License
This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.