Space-time trellis codes: Field programmable gate array approach

Mallikarjuna Gowda C. P., Raju Hajare

Abstract


This paper presents an implementation of Space-time Trellis Codes for 4-state on FPGA. To reach the very high data rates provided in STTC, a lot of expensive high-speed Digital Signal Processors (DSPs) should be employed for the real time applications, while it might not be affordable. This fact has motivated in designing dedicated hardware implementations using Field Programmable Gate Array (FPGA) with low cost and power consumption. The hardware device XC3S400, family Xilinx Spartan-3, and package PQ208 are used in this project, in which the STTC encoder and decoder utilizes maximum 10% and 22% as that of available device capacity respectively. The design has been simulated and synthesized successfully in Xilinx integrated software environment.

Keywords


Digital signal processors; FPGA; Space-time trellis codes; Squared euclidean distance; Viterbi decoding algorithm

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DOI: http://doi.org/10.11591/ijres.v9.i3.pp%25p
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