Design and Analysis of Gate All Around Tunnel FET based SRAM

Umesh Dutta, M. K. Soni, Manisha Pattanaik

Abstract


Tunnel FETs (TFETs) have emerged as one of the most promising devices for replacing MOSFET in designing circuits with stringent requirements particularly for Internet of Things (IoT) and Biomedical applications. In particular TFET device designed in gate-all-around (GAA) configuration exhibits higher ION/IOFF ratio and better control of the channel electrical characteristics. In this work both n-type and p-type hetero dielectric tri material gate tunnel FET device (HD-
TMGTFET device) are designed and simulated using Cogenda Visual TCAD tool and a look up table-based Verilog-A model has been designed for performing circuit simulations of SRAM cell involving these novel devices. Device simulation results show that both NTFET and PTFET devices exhibits excellent ION/IOFF ratio and steep subthreshold slope. NTFET device exhibits subthreshold slope of 21.2 mV/decade and ION/IOFF ratio of 10 13 . PTFET device has ON current of the similar order as that of NTFET and has extremely low value of OFF current
of less than 1 pA. Circuit simulation results show that by using appropriateĀ  sizing of transistors in outward NTFET access transistor based 6T SRAM cell leads to reliable and fast read and write operation with acceptable values of read and write noise margin. 6T TFET SRAM cell achieves leakage power reduction by 77.5% as compared to 8T TFET SRAM making it a favorable choice for memory design.


Keywords


Subthreshold Slope; BTBT model; Leakage Current; High-K dielectric; Miller Capacitances, Ambipolarity Static Random Access Memory (SRAM); Leakage Current



DOI: http://doi.org/10.11591/ijres.v9.i2.pp%25p
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