A detailed scrutiny and reasoning on VLSI adder circuits and architectures

K Mariya Priyadarshini, P. Ratna Bhaskar, Dr.R.S. Earnest Ravindran


In this paper a survey on recent developments in the design of binary adders is done. Adders are the core cells of any arithmetic unit which define the speed of any processor. The motivation of this paper is to focus on different kinds of architectures of higher order binary adders that provide high speed, less power to increase the level of integration on any integrated circuits(IC). Though there are many algorithms proposed for improving the speed of an adder the challenges still remain in designing fast and accurate adders. At the architectural level we review six different adders for high speed and reducing power consumption.


carry propagation delay, fast adder principles, carry selection, carry skip, prefix adders.

DOI: http://doi.org/10.11591/ijres.v9.i2.pp%25p
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