A body bias technique for low power full adder using XOR gate and pseudo NMOS transistor

Pritty Pritty, Manoj Kumar, Mariyam Zunairah

Abstract


Power dissipation is a major issue in digital circuit design. As technology into developed into range, power and delay becomes vital nanometer parameters to ameliorate the performance of the circuit. To minimize the power consumption many low power techniques such as MTCMOS, stacking, body biasing techniques have been reported. In this paper, a new pseudo NMOS adder circuits have presented. It has designed using transmission gate and body bias technique. Simulation has been accomplished by using SPICE tool. The simulation result show the validity of the proposed techniques is reduces power dissipation from 0.367 mW to 0.267 mW and PDP reduced from 19.311pJ to 13.311pJ. Overall improvement of 29% in power consumption and 30% in PDP has obtained.

Keywords


Body biasing, Full adder, Pass transmission logic, Pseudo NMOS, XOR gate

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DOI: http://doi.org/10.11591/ijres.v8.i3.pp%25p
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Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.