Energy and Area Effective Hardware Design of Lifting Approach Discrete Wavelet Transform

Abstract

This paper presents low power Discrete Wavelet Transform DWT architecture, comprising of forward and inverse multilevel transform for 5/3 lifting scheme LS based wavelet transform filter. This LS filter consists of integer adder units and binary shifter rather than multiplier and divider units as in the convolution based filters; hence it is more adaptable to energy efficient hardware performance. The proposed architecture is described using the VHDL based methodology. This VHDL code has been simulated and synthesized to achieve the gate level building design which can be organized to be effectively developed in hardware environment. The Quartus II 9.1 software synthesis tools were employed to implement 2D-DWT VHDL codes in Altera Development board DE2, with Cyclone II FPGA device. The proposed LS wavelet architectures can be attained by focusing on the physical FPGA devices to considerably decrease the needed hardware expenditure and power consumption of the design. The utilized logic and register elements of the architecture are 127 slices (only 1%) usage from 33216 and the architecture consumes only 0.033 W. Simulations were performed using different sizes of gray scale images that authenticate the proposed design and attain a speed performance appropriate for numerous real-time applications.