Design of Low Power Dual Dynamic Node Flip-Flop Using Sleep Transistor with NMOS

Ajeesh Kumar, N. Saraswathi


This paper introduces a Low Power Dual DynamicNode FlipFlop(DDFF) using Sleep Transistor with NMOS. Theproposed design retains the logic level till the end of evaluation and pre-charge mode. The low power DDFF architecturethat combines the advantages of dynamic and static CMOSstructures. The Sleep Transistors approach are used for leakagepower reduction. It reduces leakage current in ideal mode.The performance of the proposed flip flop was compared withthe conventional dual dynamic node flip flop (DDFF) in 90nmCMOS technology with 1.2v supply voltage at room temperatures.Also, conventional DDFF and DDFF using Sleep Transistor withNMOS are compared with other complicated designs and realizesby a 4-bit Johnson up and down counter. The performanceimprovements indicates that the proposed designs are suited formodern high-performance CMOS circuits where leakage powerand power delay product overhead are of major concern

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