A low power comparator utilizing MTSCStack, DTTS, and bulk-driven techniques

Received Jun 4, 2021 Revised Jul 27, 2021 Accepted Aug 13, 2021 Comparator is one of the main blocks that play a vital task in the performance of analog to digital converters (ADC) in all modern technology devices. High-speed devices with low voltage and low power are considered essential for industrial applications. The design of a low-power comparator with high speed is required to accomplish the requirements mostly in electronic devices that are necessary for high-speed ADCs. However, a highspeed device that leads the scaling down of CMOS process technology will consume more power. Thus, power reduction techniques such as multithreshold super cut-off stack (MTSCStack), dual-threshold transistor stacking (DTTS), a bulk-driven, and a bulk-driven differential pair were studied in this work. This study aims to find and build the combination of these techniques to produce a comparator that can operate in low power without compromising existing performance using the 0.13-μm CMOS process. A comparator with a combination of MTSCStack, DTTS, and NMOS bulk-driven differential pair shows the most promising result of 6.29 μW for static power, 17.15 μW for dynamic power, and 23.44 μW for total power.


INTRODUCTION
For years, the consumer electronics such as phone, laptop, or any other IC-based devices have dramatically enjoyed a better performance in terms of speed, due to the increasing amount of the transistors that can fit into the same size of such devices. The higher number of transistors per unit area that resides in such devices was made possible due to the scaling down of IC technology namely CMOS technology. However, this smaller transistor comes with a problem of power dissipation known as leakage power [1], [2]. Leakage power is now a dominating component of total power consumption in IC-based devices. So, researchers have started introducing the state-of-the-art techniques to develop a low power circuit in almost all the new consumer electronics products.
For instance, a handset always has a component known as the transceiver chip. One vital component in that chip is analog to digital converters or known as analog to digital converters (ADC). They are used to process, transport, or store any analog signal in digital form. ADC mainly consists of a comparator. According to past work, the comparator is responsible for about 70% of the ADC speed [3], [4]. ADC is currently adopted in many application fields to improve the digital system, which achieves superior performance concerning analog solutions. As reported by [5], [6], the impact of leakage power to the total power consumption is steadily increasing due to the scaling down of CMOS technology. Thus, the fundamental principle of low power is to start with less leakage current. To reduce the dynamic and static power consumption, low power techniques must be applied to the integrated circuit. The possible techniques are multi-threshold super cut-off stack (MTSCStack), dual-threshold transistor stacking (DTTS), and bulk-driven [7]- [9]. These techniques were then studied and applied in the design of the comparator circuit [10] and the details are presented in the following section.

RESEARCH METHOD
This section provides the circuit schematic of the chosen five circuits for discussion out of eight combinations used for this study. The eight combinations consist of a range of one to three chosen techniques combined into one circuit.

Conventional comparator
In this project, a 3-stage comparator utilizing a 2-stage CMOS operational amplifier (op-amp) with the output inverter is used. Figure 1 shows a circuit of the reference (main) comparator used in this study [9], 10]. The circuit provides a high speed with moderate power consumption and it is easier to be optimized due to its simple architecture.
The first stage of the conventional comparator is the NMOS differential pair which are NM1 and NM2. The differential pair is driven by tail current transistor NM5. An NMOS differential is chosen because the NMOS transistor has higher mobility compared to the PMOS transistor. Besides, the NMOS transistor also more efficient as conductivity is proportional to mobility. As the mobility of the carriers in an NMOS is approximately 2 to 3 times higher than PMOS, the PMOS must be 2 to 3 times the size of the NMOS. Therefore, the length of PM3 and PM4 is 0.26-µm in which twice the value of NM1 and NM2. Input voltage (VIN) and reference voltage (VREF) are applied to transistor NM1 and NM2 respectively. The range of input voltage applied is from 0V to 0.9 V and the reference voltage is set to 0.45 V based on (1). The bias voltage of the transistor NM5 which acts as the tail current transistor is 0.35 V. When the applied bias is slightly less than VTH the NMOS operates in a subthreshold region where the channel beneath the gate is weakly inverted. Equation (2) was used to determine the size of the tail-current transistor NM5 and bias-current, IBIAS was set as 3 µA. The transistor length was 130-nm and the assumption was made where VDSAT is 0.5 V. The transistor is set to be in the saturation to experience a stable and higher gain. In the second stage, a common source amplifier, PM6 provides a high and total voltage gain. Meanwhile, PM3, PM4, and PM10 are the diode loads to the differential pair. The final stage consists of PM8 and NM9, the push-pull inverter is the output driver of the comparator. The inverter is used to provide modest gain and increase the slew rate of the circuit [9]. Table 1 shows the length and width of all the transistors used in this conventional comparator circuit.

Comparator with DTTS and MTSCStack
DTTS is used to reduce the leakage current with less impact on the propagation delay. The leakage current can be reduced when a higher threshold voltage is assigned to some resistor in the non-critical path. Therefore, the performance can be sustained due to the low threshold voltage transistor in the critical path. A high threshold voltage is applied to the sleep transistors based on the MTCMOS technique [11]- [13]. Therefore the sleep transistor turns off during standby mode. The threshold voltage can be increased by increasing the VSB which is sourced to the bulk voltage based on (3) [14]- [18].
Where γ is a body-effect coefficient, F  is Fermi potential, VSB is a source-bulk potential difference and VTHO is threshold voltage in the absence of VSB.
In the power reduction technique, threshold voltage and leakage current are the major contributors and the relation between these two is stated in (4). The increasing threshold voltage leads to the reduction of sub-threshold leakage.
where K is Boltzmann's constant (1.38x10-23J/K), W/L is the width divided by length, n is the technology parameter, VGS is gate-source voltage, VTH is threshold voltage, and VDS is a drain-source voltage. The schematic of the comparator with the implementation of DTTS and MTSCStack technique is shown in Figure 2.
Based on Figure 2, the transistors PM8a, PM8b, NM9a, and NM9b are the sleep transistors. Transistors PM8a and NM9a are the additional transistors that build with high VTH by applying different body biasing. The size of PM8a, PM8b, NM9a, and NM9b is half of the original width size due to the force stack approach. The VBP and VBN are set 0.75 V and 0.5 V respectively. The sleep transistor is turned on during active mode and turn off during standby mode. The leakage can be reduced much lower than the conventional comparator due to the stacking effect. This is because the two transistors in series turn off together during standby mode and no current flowing through the circuit.
The second technique which is MTSCStack is introduced to reduce the leakage power in active mode and at the same time retaining the logic state of the comparator during the idle state. Compared to the conventional circuit, there are an additional four transistors which consist of two PMOS transistors (PM12 and PM15) and two NMOS transistors ( NM13 and NM14). During active mode, the sleep transistor PM12 is turned off while sleep bar transistor NM14 is turned on. Therefore the circuit operates as normal. However, the leakage current can be reduced because of the stacking effect of PM12 and NM14. While in sleep or standby mode, the sleep transistor is turned on while the sleep bar transistor is turned off. As a result, all sleep transistors turned off except PM15 and NM13 because it will give the ability to retain the logic state to the circuit. A slightly negative gate voltage is applied to the sleep transistor to reduce the leakage current. This is because the VGS will affect the sub-threshold leakage based on (4). The gate voltage for the sleep transistor and sleep bar transistor is -1.1 V and 0.78 V respectively. Transistor NM13 is designed to parallel with the PM12 sleep transistor with its source connected to VDD to maintain high value in the ideal mode. In contrast, PM15 is designed to parallel with the NM14 sleep bar transistor with its source to GND to maintain a low value in the ideal mode. Table 2 shows the width and length of all the transistors used in this circuit.

Comparator with DTTS and MTSCStack and bulk-driven current mirror
Comparator circuit with DTTS, MTSCStack, and bulk-driven current mirror technique applied is shown in Figure 3. The leakage power can be reduced using DTTS and MTSCStack techniques and the threshold voltage can be controlled using the bulk-driven current mirror technique.
The design structure of the bulk-driven PMOS current mirror with the bulks of PM1 and PM2 are tied together rather than the gates [19]- [22]. By using (5), the current across the MOSFET can be determined. Precaution must be taken that the value of VBS is such that bulk-source junction either reverse biased or slightly forward biased with VBS less than VTH to ensure the negligible bulk current in the circuit. The constant bulk source is applied to get the operation current mirror of the bulk-driven circuit, PM1, and PM2 MOSFETs. To enhance the current range, the transistor pair must be in a saturation region. It is done by connecting their gates to an appropriate value of input voltage (VIN) and reference voltage (VREF). where β = µCoxW/L, μ is the mobility of the carriers, Cox is gate oxide capacitance per unit area, W/L is the aspect ratio of MOSFET, F  is absolute fermi potential, VTH0 is zero bias threshold voltage and γ is a bodyeffect coefficient. Hence it is allowing for a significant rise in the available voltage headroom and reduces the total supply voltage of the circuit. An additional stage of an inverter (PM0 and NM0) is added in this circuit to invert the output since the first stage is based on PMOS bulk-driven current mirror. Table 3 shows the width and length of all the transistors used in this circuit.

Comparator with DTTS & MTSCStack and NMOS/PMOS bulk-driven differential pair
In these circuits, a combination of three techniques of DTTS, MTSCStack, and NMOS/PMOS bulkdriven differential pair is implemented [23]- [25]. In the bulk-driven approach, the input signals (VIN and reference voltage VREF) are applied to the bulk terminals of transistors NM1 and NM2, whereas the gate terminals of these devices are biased with a VG of 0.5 V. The channel current is modulated by the input signals applied to the bulk terminals. Figure 4 graphically shows the combination of the techniques used. For the NMOS type circuit, Figure 4(a), note that the sizing of all the transistors used in this comparator circuit is the same as in Table 2 since the components used are the same. For the PMOS type circuit, Figure 4(b), note that the sizing of all the transistors used in this comparator circuit is the same as in Table 3 since the components used are the same. Also, the inverter circuit is labeled as NM12 and PM18 instead of NM0 and PM0 (see Figure 3) but they are the same circuit.

RESULTS AND DISCUSSION
In this section, the results of the research are explained and at the same time, a comprehensive discussion is given.

Static and dynamic characteristics
Cadence virtuoso analog design environment was used to run all the simulations. The static characteristic of comparators can be simulated by using DC analysis. During the DC analysis, VIN (input voltage), has been swept to obtain the output of the comparators. The VIH (upper input), VIL (lower input), VOH (upper output), and VOL (lower output ) were extracted from the transfer curve and used in the calculation of the gain by using (6). Besides, the resolution and offset of the comparator were also calculated based on (7) and (8) respectively.
The DC response and transient response of one of the comparators are shown in Figure 5. Table 4 shows the mentioned static parameters for all the combinations of the comparators. It shows that the performance of all comparators is comparable.
For dynamic characteristics, transient analysis, with one cycle has been used to get the propagation delay. Pulse signal has been used as the input signal. The difference of input and output signal at 50% transition of logic 0 to logic 1 gives the calculation of the delay. From the transient response in Figure 5(b), the delay for each design was calculated. Table 5 shows the propagation delays of all comparators. It is observed that the lowest delay is obtained from the conventional comparator, while the highest delay was coming from the comparator with MTSCStack, DTTS, and PMOS bulk-driven differential pair. The results also show that the comparators with PMOS transistors experience the worst delay i.e., a comparator with PMOS bulk-driven differential pair and comparator with MTSCStack, DTTS, and PMOS bulk-driven differential pair.

Power consumption
Pulse input signal has been used at the input when getting the dynamic power, recorded when there was a switching activity. The dynamic power of a comparator is the difference between total power consumption and static power. On the opposite, a static DC voltage has been applied as an input signal when getting a static power, produced by the leakage current that happened in a transistor. The supply voltage used was 0.9 V because it is the most suitable value for obtaining stable power consumption and propagation delay. If the supply voltage assigned is higher, the propagation delay will be lower and power consumption will be higher. Since the objective of the work is to design a low power comparator, the low power supply was chosen. Figure 6 shows the results of the power consumption for the comparators. Figure 6(a) shows conventional comparator and comparator with MTSCStack and DTTS have very low static power compared to the others. For dynamic power, a comparator with MTSCStack, DTTS and PMOS, or NMOS bulk-driven differential pair have shown that there is a very significant reduction of dynamic power compared to conventional comparator or comparator with MTSCStack and DTTS. However, the low power reduction achieved at the expense of higher propagation delay compared to conventional comparator as can be observed in Table 5. Figure 6(b) shows the total power consumption of the comparators.

CONCLUSION
In this work, power reduction methods or techniques are known as MTSCStack, DTTS, bulk-driven current mirror, NMOS, and PMOS bulk-driven differential pair were studied. Though MTSCStack and DTTS were often used in digital circuits previously, this work has shown that they are also fit in analog circuits. However, compared to the reference comparator, proposed comparators relatively, have higher propagation delay. These factors will slightly influence the speed performance of the comparators.
Nonetheless, this work has proved that out of seven proposed comparators, the combination of MTSCStack, DTTS, and NMOS bulk-driven differential pair showed the best performance of low power analog circuit in general and comparator in specific without compromising the other parameters of the comparator such as propagation delay, offset, and resolution.