Co-simulation of linear congruential generator by using Xilinx system generator and MATLAB Simulink

Received May 12, 2020 Revised Aug 8, 2020 Accepted Jan 10, 2021 Arbitrary numerals are utilized in a wide range of uses. Genuine arbitrary numeral generators are moderate and costly for some applications while pseudo arbitrary numeral generators (RNG) do the trick for most applications. This paper fundamentally concentrates around the cosimulation of the linear congruential generator (LCG) model utilizing the Xilinx System generator and checking on Matlab Simulink. The design is obtained from the LCG calculation offered by Lehmer. Word lengths decrease strategy has been utilized to streamline the circuit. Simulation has been done effectively. The effective N bit LCG is structured and tried by utilizing demonstrating in MatLab Simulink. The Co-simulation of the model is done by utilizing the Xilinx system generator. This paper conducts an exhaustive search for the best arbitrary numeral generator in a full period linear congruential generator (LCG) with the largest prime numbers.


INTRODUCTION
Arbitrary numerals have been utilized in everyday exercises from the time when occasions prior. These days, a little and modest child's puppet holding an arbitrary numeral based circuit in it. For instance, in a model like cell phones will buzz various kinds of tones by pressing the same key more than one time. A few arbitrary numerals of hypotheses have been presented over the most recent quite a few years. LCG (Linear congruential generator) that presented by Lehmer in 1954 is the ancient [1] and generally utilized pseudoarbitrary numeral generator (PNG) [2]. Park and Mill's operators recommend great bounds for LCG [3]. The recommendation is utilized in MatLab for producing similar kind of arbitrary numerals [4]. Numerous new arbitrary numeral generators were suggested and utilized in numerous suplications. Linear feedback shift register, Wichmann-Hill, Blum Blum Shub, Complementary multiply with carry, ISAAC (cipher), Inversive congruential generator, Lagged Fibonacci generator, Mersenne twister, Maximal periodic reciprocals, Naor-Reingold Pseudoarbitrary Function, Multiply-with-carry, Well Equidistributed Long-period Linear, RC4 PRGA, and Xor shift are few familier methods [5][6][7][8]. Equipment for creating arbitrary numerals accessible just as its calculation. The equipment has been utilized since 2008. LETech is the quickest among all hardware for generating arbitrary numerals, this method has been used since 2008 [9,10]. Research for finding the reasonable algorithm of generating an arbitrary numeral is well building upfield as of recently. Numerous specialists utilize FPGA (field programmable gate arrays) for testing their views. At first, the algorithm of LCG joined with the Monte-Carlo method has been utilized for producing non-uniform arbitrary  [11]. Later, the circuit of arbitrary numeral generator is tested and implemented on FPGA [12]. Here the subtractor block has been removed and presenting the novel structure implemented on MatLab Simulink with the help of Xilinx building blocks for LCG algorithm.

LINEAR CONGRUENTIAL GENERATOR
There is a common technique to generate an arbitrary numeral called the linear congruential generator. This knowledge was introduced by Lehmer according to a sequential formula in (1) [1].
where 'a' is multiplier, 'm' is modulus, 'c' is increment. Factors a, m, and c must be selected wisely to evade reappearance of like numerals before m [6][7][8]. The better result can be achieved by selecting c=0 is specified by Park & Miller [3]. The modulus value 'm' must be a largest prime number; multiplier 'a' will be a number must be less than m-1. The generated arbitrary numerals will be less than or equal to modulus m.

LCG CIRCUIT DESIGN
Common Circuit of LCG is shown in Figure 1 LCG activity in all (seed is neglected). It needs adder, multiplier, subtractor and comparator functional units. The multiplier is utilized to find preceding arbitrary value 'x' with 'a', perorm the addition by incrementing 'c'. After that, use the value to find the modulus 'm'. The numeral is reflected as an arbitrary numeral if that numeral is lesser or equal to 'm'. If the numeral is greater than 'm' then it's subtracted with 'm'. The resultant of this is considered an arbitrary numeral. The block diagram represented in Figure 1 contains operations like addition, multiplication, addition, comparison and subtraction. To simplify the work process; the circuit is intended using the 'word lengths' lessening method that has recommended in [13][14][15][16][17][18][19][20][21][22][23][24][25]. Then comparator and subtractor blocks can be merged, as shown in Figure 2.

CO-SIMULATION OF THE MODEL USING SYSTEM GENARATOR
The fundamental objective is to carry out equipment co-recreation of the Simulink model utilizing an HDL coder for LCG. Figure 3, demonstrates the HDL coder, Xilinx blocks, and Simulink model for equipment coreproduction. The Xilinx Blockset is a public library for a piece, cycle genuine recreation and backups tradition capacities. The HDL coder utilizes Xilinx altered IP centers and creates a synthesizable code. Before ongoing execution of the LCG utilizing FPGA, the model testing of the plan is finished by utilizing a HDL coder. The model testing of the LCG is confirmed effectively by utilizing the VHDL code created from the HDL coder. The framework generator creates a piece record for FPGA and utilized VIRTEX II FPGA board for the execution reason.

RESULTS OF HARDWARE CO SIMULATION
Design for PRNGs is based on LCG which can be constructed in such a way as to have optimal statistical and periodical properties using co-simulation. Simulation results are shown in Figure 4 and corresponding signal observed in Oscilloscope is shown in Figure 5 respectively. Simulation results of LCG using Xilinx. Co-Simulation results for 4-bit, 8-bit, 16-bit and 32-bit are shown in Figure 6, Figure 7, Figure  8 and Figure 9 respectively.

CONCLUSION
The simulation results help us to verify the functionality of the model. The model is designed for the LCG, which works fine and performance is better with implementation of FPGA as well as on Co-simulation method. The results that can be obtained are close to the theoretical analysis of specifications chosen for the model. As the numeral of bits increases the complexity increases with Xilinx simulation. This problem is solved using Xilinx system generator based design implementation. It helps us to reduce the time and complexity for writing HDL programs for large data size. The process can be used for larger numeral signals with a higher value of m. Simulation and practical results of 8-bit LCG using HDL code was also recoreded. Co-Simulation results of 4-bit, 8-bit, 16-bit, and 32-bit is verified recorded and compared with HDL based results.