Ultra high speed full adder for biomedical applications

Received Dec 10, 2020 Revised Jan 10, 2021 Accepted Jan 20, 2021 In the field of biomedical engineering high performance CPU for digital signal processing plays a significant role. Frequency efficient circuit is a paramount requirement for the portable digital devices employing various digital processors. In this work a novel high speed one-bit 10T full adder with complemented output was described. The circuit was constructed with XOR gates which were built using two CMOS transistors. The XOR gate was constructed using 2T multiplexer circuit style. It was observed that power consumption of the designed circuit at 180nm with supply voltage 1.8V is 183.6 uW and delay was 1.809 ps whereas power consumption at 90nm with supply voltage 1.2V is 25.74 uW and delay was 8.245 ps. The observed Power Delay Product (PDP) in 180nm (at supply voltage 1.8V) is 0.33 and in 90nm (at supply voltage 1.2V) is 0.212. The work was extended by implementing a 32-bit Ripple Carry Adder (RCA) and was found that the delay at 180nm is 93.7ps and at 90nm is 198ps. The results were drawn at 180nm and also 90nm technology using CAD tool. The results say that the present work offered significant enhancement in speed and PDP compared with existing designs.


INTRODUCTION
Advancement in VLSI technology given path to immense development in portable digital equipments like mobile handsets, tablets, PDA's etc. The compact sizes, low power, high speed of operations are the key features of these applications. However still research had been going on to improve the performances of the applications. Every time it is a challenge for the VLSI engineers to bring tradeoff among the design entities like power consumption, delay and area of VLSI chips. Since, addition is basic operation that is extensively used in most of the processors, this module plays important role in arithmetic operations like addition, multiplication, division and address formation [1,2]. The power delay product (PDP) of the adder affects the total performance of the system. Considering this fact, the full adders are to be designed with high speed and less power [3].
Any digital processor consists of a full adder circuit at its initial levels of architecture. The full adder designs has the effect on the all the operations of processors like DSP architectures and microprocessors. The existing 28T full adder was designed using CMOS technology which consists of 28 transistors [4]. The demerits of 28 transistors CMOS full adder was its need of buffers and its high impedance and the merit is robustness against size of the transistors and scaling of voltage levels [5]. The output swing in complementary pass transistor (CPL) style full adder (32 transistors) was good but cannot be used for low  [6,7]. The demerit of output degradation in CPL was eliminated in transmission gate adder (20 transistors). In the proposed circuit the full adder was constructed using only 10 transistors which promise full swing voltage levels at its outputs [8].The proposed circuit produced complemented sum and carry outputs. It used basic building blocks where each block consists of 2 transistor multiplexer circuit which produced XOR output as shown in Figure 2(a). The sum and carry outputs generated were given to the inverter circuits to produce full swing complemented sum and carry outputs [9][10][11][12]. The main aim of the proposed design was to show efficiency in the delay, PDP and number of transistors compared to other existing full adders. The proposed design was implemented by varying the width of the transistors in order to achieve full voltage swing at 90 and 180nm technology using SPICE tool as shown in Table 1. The propagation delay of the proposed circuit was 8.245 ps and the power consumption was 25.74 uW at 90nm whereas propagation delay was 1.809 ps and power consumption was 183.6 uW at 180nm technology as shown in Table 2 and Table 3.

RESEARCH METHOD
The proposed design consists of five blocks: module 1, 2, 3, 4 & 5. Module 1, 2 & 3 consists of 2 transistor multiplexer circuit which produced XOR output as shown in Figure 1. Module 1, 2 & 4 generates the complemented sum and module 3 & 5 generates complemented carry. The width of the transistors in each module was varied such that the design entities like delay, area and PDP were optimized. The full logic swing of the output levels was obtained by varying the width of the transistors in the modules and placing the inverters at the outputs. These inverters will restore the logic levels resulted in complemented outputs. The carry output was constructed using 2 transistor multiplexer circuit only [13][14][15]. This carry output circuit consists of MP4 & MN4; the output of this carry module was connected to inverter to achieve complemented carry. The inverter connected at the output produces full swing logic levels.

CIRCUIT OPERATION
The module 1 consists of 2T XOR circuit which produced XOR output as shown in Figure 2 The sum output of module 2 was applied to inverter to give complemented sum output which has full swing voltage level. Module 3 also consists of 2T XOR whose inputs were Cin and B applied to MP4 & MN4 transistors where channel widths were also varied. The output of the module 3 was given to inverter which yielded complemented carry.

PERFORMANCE OF THE PROPOSED DESIGN
The proposed full adder as shown in Figure 2(b) was designed at 90 and 180nm technology. The design entities like transistor count, average power and delay was compared with previous designs [18,19]. It was observed that in this design the propagation delay was reduced by less the number of transistors in the circuit and also due to with of the transistors as shown in Table 1.
Full voltage swing was obtained by connecting the outputs to the voltage restoration circuit (inverter).The proposed adder was compared with other adders. The results were compared by simulating all the adders in 90 and 180nm technology. The performance parameters like PDP, power and operating speed with the supply voltage 1.8V and 1.2V are drawn at 180nm and 90nm respectively and compared with existing designs. The comparisons are shown in the Tables 2 and Table 3.

CALCULATION OF PROPAGATION DELAY AND POWER DISSIPATION
The propagation delay in an adder is governed by the overall speed of the entire arithmetic unit of the processors or in other words overall speed of the design can be calculated using propagation delay. In this design the carry was generated using 2T multiplexer logic circuit which acted like an XOR gate. The carry inputs (Cin) were given to this XOR gate (ie., module 2). To overcome the problem of voltage swing at the output the carry output was given to the inverter circuit which acted as level restorer. In this design the carry input was propagated through only one module ie., module 2 which acted as XOR gate as said above and hence leads to very less propagation delay [20]. However the widths of the transistors at 180nm and 90nm technology being changed to reduce the propagation delay [21].
Power consumption in VLSI circuits is due to switching of the transistors and short circuits. The total power is given as Ptotal = Vdd. Fclk .∑iVswing.Cload.Pi + Vdd.∑iIsc + Vdd.Il Where Vdd = supply voltage, Vswing = voltage swing at the output Cload =i load capacitance Fclk = frequency of operation Isc= short circuit current Il= leakage current.
The average power consumption was calculated for the proposed design at 180nm and 90nm technologies. The supply voltage at 180nm and 90nm technologies was 1.8v and 1.2v respectively. The widths of the transistors in the proposed design at 180nm and 90nm technologies were 200nm and 120nm respectively. The power of the design at two different technologies was given in the Tables 2 and Table 3. It was observed that average power consumption of the design at 90nm was less when compared to 180nm technology [22,23].

IMPLEMENTATION OF 32-BIT RCA
The work was extended by implementing a 32-bit RCA in 180 and 90 nm technologies. The sum and carry outputs of full adder in each stage depend on carry of previous stage which results in producing the final carry with more delay. In this circuit the delay was very less compared to other standard designs. Overall delay of the RCA adder can be minimized by implementing using the design. From the obtained results it is observed that the overall delay produced by the 32-bit RCA in 90nm technology (at 1.2V supply voltage) is 198.8ps and in180nm technology (at 1.8V supply voltage) is 93.7ps. 32-bit fulladder using 1-bit full adder multiplexer circuit as shown in Figure 3.   [24]. The simulation process was carried out by parametric analysis of the widths of the transistors so that proper voltage swing was obtained with less delay. The circuit design and simulation process was compromised in reducing the power consumption. However the delay of the circuit was greatly optimized when compared to all other designs. The power delay product (PDP) was also optimized due to very low propagation delay [25].
The proposed fulladder circuit was constructed using 10 transistors. The schematic of the fulladder was designed at 180nm and 90nm CMOS technologies using Cadence Virtuoso tool. Table 1 shows the widths of the transistors at 180nm and 90nm technologies. Tables 2 and 3 show the performance comparison regarding PDP, propagation delay and power consumption. From Table 2 it can be observed that the PDP was 35.4% efficient with the best design report at 180nm. Also from the Tables 2 & 3 the propagation delay was very less compared with all other circuits at 180 nm & 90nm technology as shown in Figures 5 and 6. The Figure 4 shows the comparison of PDP of various fulladders with the present work. In this paper a 32-bit RCA as shown in Figure 3 was implemented as an extension to the proposed work. In the implemented RCA only the delay was calculated. The performance evaluation was carried out at 180nm and 90nm technologies. The results shown that the overall delay produced by the 32-bit RCA in 90nm technology (at 1.2V supply voltage) is 198.8ps and in180nm technology (at 1.8V supply voltage) is 93.7ps.

CONCLUSION
Here a delay efficient adder was introduced. The design was carried out using SPICE tool at 90 and 180nm technology. It was observed from the results that proposed circuit offers improved propagation delay & PDP. From simulations it can be said that the adder circuit is 35.4% efficient in PDP wrt best design at 180nm technology and 10.4% efficient in delay wrt best design at 90nm technology. The circuit was further used to implement a 32-bit RCA. The propagation delay of 32-bit RCA at 100MHz in 90nm technology (at 1.2V supply voltage) is 198.8ps and in180nm technology (at 1.8V supply voltage) is 93.7ps.